Merge branch 'master' into verilog-ams
This commit is contained in:
Stephen Williams
commit
f588656dd5
96
Statement.h
96
Statement.h
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@ -1,7 +1,7 @@
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#ifndef __Statement_H
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#define __Statement_H
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/*
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* Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
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* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -18,9 +18,6 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: Statement.h,v 1.44 2007/05/24 04:07:11 steve Exp $"
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#endif
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# include <string>
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# include "svector.h"
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@ -417,6 +414,7 @@ class PRepeat : public Statement {
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virtual NetProc* elaborate(Design*des, NetScope*scope) const;
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virtual void elaborate_scope(Design*des, NetScope*scope) const;
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virtual void elaborate_sig(Design*des, NetScope*scope) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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@ -462,6 +460,7 @@ class PWhile : public Statement {
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virtual NetProc* elaborate(Design*des, NetScope*scope) const;
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virtual void elaborate_scope(Design*des, NetScope*scope) const;
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virtual void elaborate_sig(Design*des, NetScope*scope) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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@ -469,93 +468,4 @@ class PWhile : public Statement {
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Statement*statement_;
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};
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/*
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* $Log: Statement.h,v $
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* Revision 1.44 2007/05/24 04:07:11 steve
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* Rework the heirarchical identifier parse syntax and pform
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* to handle more general combinations of heirarch and bit selects.
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*
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* Revision 1.43 2007/03/05 05:59:10 steve
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* Handle processes within generate loops.
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*
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* Revision 1.42 2005/12/05 21:21:18 steve
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* Fixes for stubborn compilers.
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*
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* Revision 1.41 2004/12/11 02:31:25 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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* down this path.
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*
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* Revision 1.40 2004/02/20 18:53:33 steve
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* Addtrbute keys are perm_strings.
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*
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* Revision 1.39 2004/02/18 17:11:54 steve
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* Use perm_strings for named langiage items.
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*
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* Revision 1.38 2003/05/19 02:50:58 steve
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* Implement the wait statement behaviorally instead of as nets.
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*
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* Revision 1.37 2003/01/30 16:23:07 steve
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* Spelling fixes.
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*
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* Revision 1.36 2002/08/12 01:34:58 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.35 2002/06/04 05:38:44 steve
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* Add support for memory words in l-value of
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* blocking assignments, and remove the special
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* NetAssignMem class.
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*
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* Revision 1.34 2002/05/26 01:39:02 steve
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* Carry Verilog 2001 attributes with processes,
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* all the way through to the ivl_target API.
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*
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* Divide signal reference counts between rval
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* and lval references.
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*
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* Revision 1.33 2002/04/21 22:31:02 steve
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* Redo handling of assignment internal delays.
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* Leave it possible for them to be calculated
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* at run time.
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*
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* Revision 1.32 2002/04/21 04:59:07 steve
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* Add support for conbinational events by finding
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* the inputs to expressions and some statements.
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* Get case and assignment statements working.
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*
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* Revision 1.31 2001/12/03 04:47:14 steve
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* Parser and pform use hierarchical names as hname_t
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* objects instead of encoded strings.
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*
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* Revision 1.30 2001/11/22 06:20:59 steve
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* Use NetScope instead of string for scope path.
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*
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* Revision 1.29 2000/09/09 15:21:26 steve
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* move lval elaboration to PExpr virtual methods.
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*
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* Revision 1.28 2000/09/03 17:58:35 steve
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* Change elaborate_lval to return NetAssign_ objects.
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*
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* Revision 1.27 2000/07/26 05:08:07 steve
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* Parse disable statements to pform.
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*
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* Revision 1.26 2000/05/11 23:37:26 steve
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* Add support for procedural continuous assignment.
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*
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* Revision 1.25 2000/04/22 04:20:19 steve
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* Add support for force assignment.
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*
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* Revision 1.24 2000/04/12 04:23:57 steve
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* Named events really should be expressed with PEIdent
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* objects in the pform,
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*
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* Handle named events within the mix of net events
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* and edges. As a unified lot they get caught together.
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* wait statements are broken into more complex statements
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* that include a conditional.
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*
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* Do not generate NetPEvent or NetNEvent objects in
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* elaboration. NetEvent, NetEvWait and NetEvProbe
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* take over those functions in the netlist.
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*/
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#endif
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12
elab_sig.cc
12
elab_sig.cc
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@ -758,6 +758,18 @@ void PForStatement::elaborate_sig(Design*des, NetScope*scope) const
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statement_->elaborate_sig(des, scope);
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}
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void PRepeat::elaborate_sig(Design*des, NetScope*scope) const
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{
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if (statement_)
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statement_->elaborate_sig(des, scope);
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}
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void PWhile::elaborate_sig(Design*des, NetScope*scope) const
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{
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if (statement_)
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statement_->elaborate_sig(des, scope);
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}
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/*
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* Elaborate a source wire. The "wire" is the declaration of wires,
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* registers, ports and memories. The parser has already merged the
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