Fix VHDL naming collisions with modules

This fixes a bug where the renaming rules for modules
would generate entity names that collided with already
existing module names.

tgt-vhdl/scope.cc

@@ -387,7 +387,7 @@ static void replace_consecutive_underscores(string& str)
 }
 
 // Return a valid VHDL name for a Verilog module
-string valid_entity_name(const string& module_name)
+static string valid_entity_name(const string& module_name)
 {
    string name(module_name);
    replace_consecutive_underscores(name);
@@ -395,7 +395,17 @@ string valid_entity_name(const string& module_name)
       name = "Mod" + name;
    if (*name.rbegin() == '_')
       name += "Mod";
-   return name;
+
+   ostringstream ss;
+   int i = 1;
+   ss << name;
+   while (find_entity(ss.str())) {
+      // Keep adding an extra number until we get a unique name
+      ss.str("");
+      ss << name << i++;
+   }
+   
+   return ss.str();
 }
 
 // Make sure a signal name conforms to VHDL naming rules.
@@ -840,7 +850,7 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth)
    arch->set_comment(ss.str());
    ent->set_comment(ss.str());
    
-   remember_entity(ent);
+   remember_entity(ent, scope);
 }
 
 /*

tgt-vhdl/state.cc

@@ -66,6 +66,10 @@ struct signal_defn_t {
 // encountered and hence it will appear first in the output file.
 static entity_list_t g_entities;  
 
+// Store the mapping of ivl scope names to entity names
+typedef map<string, string> scope_name_map_t;
+static scope_name_map_t g_scope_names;
+
 typedef std::map<ivl_signal_t, signal_defn_t> signal_defn_map_t;
 static signal_defn_map_t g_known_signals;
 
@@ -151,7 +155,7 @@ struct cmp_ent_name {
 
 // Find an entity given its name.
 vhdl_entity* find_entity(const string& name)
-{
+{   
    entity_list_t::const_iterator it
       = find_if(g_entities.begin(), g_entities.end(),
                 cmp_ent_name(name));
@@ -170,13 +174,18 @@ vhdl_entity* find_entity(const ivl_scope_t scope)
 {
    assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
 
-   return find_entity(valid_entity_name(ivl_scope_tname(scope)));
+   scope_name_map_t::iterator it = g_scope_names.find(ivl_scope_tname(scope));
+   if (it != g_scope_names.end())
+      return find_entity((*it).second);
+   else
+      return NULL;
 }
 
 // Add an entity/architecture pair to the list of entities to emit.
-void remember_entity(vhdl_entity* ent)
+void remember_entity(vhdl_entity* ent, ivl_scope_t scope)
 {
    g_entities.push_back(ent);
+   g_scope_names[ivl_scope_tname(scope)] = ent->get_name();
 }
 
 // Print all VHDL entities, in order, to the specified output stream.

tgt-vhdl/state.hh

@@ -38,7 +38,7 @@ const std::string &get_renamed_signal(ivl_signal_t sig);
 ivl_signal_t find_signal_named(const std::string &name, const vhdl_scope *scope);
 
 // Manage the set of VHDL entities
-void remember_entity(vhdl_entity *ent);
+void remember_entity(vhdl_entity *ent, ivl_scope_t scope);
 vhdl_entity* find_entity(const ivl_scope_t scope);
 vhdl_entity* find_entity(const std::string& name);
 void emit_all_entities(std::ostream& os, int max_depth);

tgt-vhdl/vhdl_target.h

@@ -28,7 +28,6 @@ ivl_design_t get_vhdl_design();
 vhdl_var_ref *nexus_to_var_ref(vhdl_scope *arch_scope, ivl_nexus_t nexus);
 vhdl_var_ref* readable_ref(vhdl_scope* scope, ivl_nexus_t nex);
 string make_safe_name(ivl_signal_t sig);
-string valid_entity_name(const string& module_name);
    
 int draw_stask_display(vhdl_procedural *proc, stmt_container *container,
                        ivl_statement_t stmt, bool newline = true);