Add some more always_ff synth checks
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Cary R
parent
e6f957b0b6
commit
3f24557e90
129
elaborate.cc
129
elaborate.cc
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@ -6198,6 +6198,132 @@ bool Design::check_proc_delay() const
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return result;
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}
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static void print_nexus_name(const Nexus*nex)
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{
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for (const Link*cur = nex->first_nlink(); cur; cur = cur->next_nlink()) {
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if (cur->get_dir() != Link::OUTPUT) continue;
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const NetPins*obj = cur->get_obj();
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// For a NetNet (signal) just use the name.
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if (const NetNet*net = dynamic_cast<const NetNet*>(obj)) {
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cerr << net->name();
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return;
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// For a NetPartSelect calculate the name.
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} else if (const NetPartSelect*ps = dynamic_cast<const NetPartSelect*>(obj)) {
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assert(ps->pin_count() >= 2);
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assert(ps->pin(1).get_dir() == Link::INPUT);
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assert(ps->pin(1).is_linked());
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print_nexus_name(ps->pin(1).nexus());
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cerr << "[]";
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return;
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// For a NetUReduce calculate the name.
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} else if (const NetUReduce*reduce = dynamic_cast<const NetUReduce*>(obj)) {
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assert(reduce->pin_count() == 2);
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assert(reduce->pin(1).get_dir() == Link::INPUT);
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assert(reduce->pin(1).is_linked());
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switch (reduce->type()) {
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case NetUReduce::AND:
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cerr << "&";
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break;
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case NetUReduce::OR:
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cerr << "|";
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break;
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case NetUReduce::XOR:
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cerr << "^";
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break;
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case NetUReduce::NAND:
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cerr << "~&";
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break;
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case NetUReduce::NOR:
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cerr << "~|";
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break;
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case NetUReduce::XNOR:
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cerr << "~^";
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break;
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case NetUReduce::NONE:
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assert(0);
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}
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print_nexus_name(reduce->pin(1).nexus());
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return;
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} else if (const NetLogic*logic = dynamic_cast<const NetLogic*>(obj)) {
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assert(logic->pin_count() >= 2);
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assert(logic->pin(1).get_dir() == Link::INPUT);
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assert(logic->pin(1).is_linked());
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switch (logic->type()) {
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case NetLogic::NOT:
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cerr << "~";
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break;
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default:
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// The other operators should never be used here,
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// so just return the nexus name.
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cerr << nex->name();
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return;
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}
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print_nexus_name(logic->pin(1).nexus());
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return;
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}
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// Use the following to find the type of anything that may be missing:
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// cerr << "(" << typeid(*obj).name() << ") ";
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}
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// Otherwise just use the nexus name so somthing is printed.
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cerr << nex->name();
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}
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static void print_event_probe_name(const NetEvProbe *prb)
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{
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assert(prb->pin_count() == 1);
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assert(prb->pin(0).get_dir() == Link::INPUT);
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assert(prb->pin(0).is_linked());
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print_nexus_name(prb->pin(0).nexus());
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}
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static void check_event_probe_width(const LineInfo *info, const NetEvProbe *prb)
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{
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assert(prb->pin_count() == 1);
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assert(prb->pin(0).get_dir() == Link::INPUT);
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assert(prb->pin(0).is_linked());
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if (prb->edge() == NetEvProbe::ANYEDGE) return;
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if (prb->pin(0).nexus()->vector_width() > 1) {
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cerr << info->get_fileline() << " Warning: Synthesis wants "
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"the sensitivity list expressions for '";
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switch (prb->edge()) {
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case NetEvProbe::POSEDGE:
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cerr << "posedge ";
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break;
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case NetEvProbe::NEGEDGE:
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cerr << "negedge ";
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break;
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default:
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break;
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}
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print_nexus_name(prb->pin(0).nexus());
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cerr << "' to be a single bit." << endl;
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}
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}
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static void check_ff_sensitivity(const NetProc* statement)
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{
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const NetEvWait *evwt = dynamic_cast<const NetEvWait*> (statement);
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// We have already checked for and reported if the first statmemnt is
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// not a wait.
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if (! evwt) return;
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for (unsigned cevt = 0; cevt < evwt->nevents(); cevt += 1) {
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const NetEvent *evt = evwt->event(cevt);
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for (unsigned cprb = 0; cprb < evt->nprobe(); cprb += 1) {
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const NetEvProbe *prb = evt->probe(cprb);
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check_event_probe_width(evwt, prb);
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if (prb->edge() == NetEvProbe::ANYEDGE) {
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cerr << evwt->get_fileline() << " Warning: Synthesis "
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"requires the sensitivity list of an "
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"always_ff process to only be edge "
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"sensitive. ";
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print_event_probe_name(prb);
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cerr << " is missing a pos/negedge." << endl;
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}
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}
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}
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}
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/*
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* Check to see if the always_* processes only contain synthesizable
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* constructs.
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@ -6211,6 +6337,9 @@ bool Design::check_proc_synth() const
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(pr->type() == IVL_PR_ALWAYS_LATCH)) {
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result |= pr->statement()->check_synth(pr->type(),
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pr->scope());
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if (pr->type() == IVL_PR_ALWAYS_FF) {
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check_ff_sensitivity(pr->statement());
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}
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}
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}
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return result;
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