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Spelling fixes 

only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
This commit is contained in:
Larry Doolittle 2008-01-29 12:19:59 -08:00 committed by Stephen Williams
parent 31afec57b1
commit d9ac146b8f
60 changed files with 126 additions and 126 deletions
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2
BUGS.txt
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@ -76,7 +76,7 @@ In this case, if possible include not only the sample Verilog program,
but the generated netlist file(s) and a clear indication of what went
wrong. If it is not clear to me, I will ask for clarification.
* The Output is Correct, But Less Then Ideal
* The Output is Correct, But Less Than Ideal
If the output is strictly correct, but just not good enough for
practical use, I would like to know. These sorts of problems are

4
driver/globals.h
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@ -31,10 +31,10 @@ extern const char*base;
extern char* iconfig_path;
extern char* iconfig_common_path;
/* Ths is the optional -M<dependfile> value, if one was supplied. */
/* This is the optional -M<dependfile> value, if one was supplied. */
extern const char*depfile;
/* Ths is the optional -N<path> value, if one was supplied. */
/* This is the optional -N<path> value, if one was supplied. */
extern const char*npath;
/* This is the name of the output file that the user selected. */

4
driver/main.c
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@ -156,7 +156,7 @@ typedef struct t_command_file {
p_command_file cmd_file_head = NULL; /* The FIFO head */
p_command_file cmd_file_tail = NULL; /* The FIFO tail */
/* Function to add a comamnd file name to the FIFO. */
/* Function to add a command file name to the FIFO. */
void add_cmd_file(const char* filename)
{
p_command_file new;
@ -173,7 +173,7 @@ void add_cmd_file(const char* filename)
}
}
/* Function to return the top comamnd file name from the FIFO. */
/* Function to return the top command file name from the FIFO. */
char *get_cmd_file()
{
char *filename;

12
elab_expr.cc
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@ -30,7 +30,7 @@
# include "ivl_assert.h"
/*
* The default behavor for the test_width method is to just return the
* The default behavior for the test_width method is to just return the
* minimum width that is passed in.
*/
unsigned PExpr::test_width(Design*des, NetScope*scope,
@ -195,7 +195,7 @@ NetEBinary* PEBinary::elaborate_expr_base_(Design*des,
case '%':
/* The % operator does not support real arguments in
baseline Verilog. But we allow it in our extended
form of verilog. */
form of Verilog. */
if (generation_flag < GN_VER2001X) {
if (lp->expr_type()==IVL_VT_REAL || rp->expr_type()==IVL_VT_REAL) {
cerr << get_fileline() << ": error: Modulus operator may not "
@ -1379,7 +1379,7 @@ NetExpr* PEIdent::elaborate_expr_net_part_(Design*des, NetScope*scope,
return net;
}
// If the part select convers exactly the entire
// If the part select covers exactly the entire
// vector, then do not bother with it. Return the
// signal itself.
if (net->sig()->sb_to_idx(lsv) == 0 && wid == net->vector_width())
@ -1417,7 +1417,7 @@ NetExpr* PEIdent::elaborate_expr_net_idx_up_(Design*des, NetScope*scope,
if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
long lsv = base_c->value().as_long();
// If the part select convers exactly the entire
// If the part select covers exactly the entire
// vector, then do not bother with it. Return the
// signal itself.
if (net->sig()->sb_to_idx(lsv) == 0 && wid == net->vector_width())
@ -1476,7 +1476,7 @@ NetExpr* PEIdent::elaborate_expr_net_idx_do_(Design*des, NetScope*scope,
if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
long lsv = base_c->value().as_long();
// If the part select convers exactly the entire
// If the part select covers exactly the entire
// vector, then do not bother with it. Return the
// signal itself.
if (net->sig()->sb_to_idx(lsv) == (wid-1) && wid == net->vector_width())
@ -1544,7 +1544,7 @@ NetExpr* PEIdent::elaborate_expr_net_bit_(Design*des, NetScope*scope,
}
// If the vector is only one bit, we are done. The
// bit select will return the scaler itself.
// bit select will return the scalar itself.
if (net->vector_width() == 1)
return net;

2
elab_lval.cc
View File

@ -33,7 +33,7 @@
* assignment. This is common code for the = and <= statements.
*
* What gets generated depends on the structure of the l-value. If the
* l-value is a simple name (i.e., foo <= <value>) the the NetAssign_
* l-value is a simple name (i.e., foo <= <value>) then the NetAssign_
* is created the width of the foo reg and connected to all the
* bits.
*

4
elab_net.cc
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@ -163,7 +163,7 @@ NetNet* PEBinary::elaborate_net_add_(Design*des, NetScope*scope,
/* The owidth is the output width of the lpm_add_sub
device. If the desired width is greater then the width of
device. If the desired width is greater than the width of
the operands, then widen the adder and let code below pad
the operands. */
unsigned owidth = width;
@ -1122,7 +1122,7 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
/* Make the constant zero's that I'm going to pad to the
top or bottom of the left expression. Attach a signal
to its output so that I don't have to worry about it
later. If the left expression is less then the
later. If the left expression is less than the
desired width (and we are doing right shifts) then we
can combine the expression padding with the distance
padding to reduce nodes. */

2
elab_scope.cc
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@ -350,7 +350,7 @@ bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
// The initial value for the genvar does not need (nor can it
// use) the genvar itself, so we can evaluate this expression
// the same way any other paramter value is evaluated.
// the same way any other parameter value is evaluated.
NetExpr*init_ex = elab_and_eval(des, container, loop_init, -1);
NetEConst*init = dynamic_cast<NetEConst*> (init_ex);
if (init == 0) {

2
elab_sig.cc
View File

@ -159,7 +159,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
}
// Run through all the generate schemes to enaborate the
// Run through all the generate schemes to elaborate the
// signals that they hold. Note that the generate schemes hold
// the scopes that they instantiated, so we don't pass any
// scope in.

2
elaborate.cc
View File

@ -2836,7 +2836,7 @@ NetProc* PForever::elaborate(Design*des, NetScope*scope) const
}
/*
* Force is like a procedural assignment, most notably prodedural
* Force is like a procedural assignment, most notably procedural
* continuous assignment:
*
* force <lval> = <rval>

2
eval_tree.cc
View File

@ -766,7 +766,7 @@ NetEConst* NetEBComp::eval_tree(int prune_to_width)
case '<': // Less than
return eval_less_();
case '>': // Greater then
case '>': // Greater than
return eval_gt_();
default:

2
extensions.txt
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@ -59,7 +59,7 @@ types as nets.
- Ports
Module and task ports in standard verilog are restricted to logic
Module and task ports in standard Verilog are restricted to logic
types. This extension removes that restriction, allowing any type to
pass through the port consistent with the continuous assignment
connectivity that is implied by the type.

4
ivl_target.h
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@ -379,7 +379,7 @@ typedef const struct ivl_attribute_s*ivl_attribute_t;
/* DELAYPATH
* Delaypath objects represent delay paths called out by a specify
* block in the verilog source file. The destination signal references
* block in the Verilog source file. The destination signal references
* the path object, which in turn points to the source for the path.
*
* ivl_path_scope
@ -1174,7 +1174,7 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
* SEMANTIC NOTES
* The ivl_lval_width is not necessarily the same as the width of the
* signal or memory word it represents. It is the width of the vector
* it receives and assigns. This may be less then the width of the
* it receives and assigns. This may be less than the width of the
* signal (or even 1) if only a part of the l-value signal is to be
* assigned.
*

2
ivlpp/ivlpp.txt
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@ -19,7 +19,7 @@
THE IVL PREPROCESSOR
The ivlpp command is a verilog preprocessor that handles file
The ivlpp command is a Verilog preprocessor that handles file
inclusion and macro substitution. The program runs separate from the
actual compiler so as to ease the task of the compiler proper, and
provides a means of preprocessing files off-line.

2
ivlpp/lexor.lex
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@ -59,7 +59,7 @@ static int yywrap();
struct include_stack_t {
char* path;
/* If the current input is the the file, this member is set. */
/* If the current input is from a file, this member is set. */
FILE*file;
/* If we are reparsing a macro expansion, file is 0 and this

2
libveriuser/a_next.c
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@ -52,7 +52,7 @@ handle acc_next(PLI_INT32 *type, handle scope, handle prev)
/*
* The acc_next_* functions need to be reentrant, so we need to
* rescan all the items upto the previous one, then return
* rescan all the items up to the previous one, then return
* the next one.
*/
iter = vpi_iterate(vpiScope, scope); // ICARUS extension

2
libveriuser/getcstringp.c
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@ -24,7 +24,7 @@
#include <acc_user.h>
/*
* tf_getinstance implemented using equvalent acc_ routing
* tf_getinstance implemented using equivalent acc_ routing
*/
char *tf_getcstringp(int n)
{

2
libveriuser/priv.h
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@ -32,7 +32,7 @@
extern char* __acc_newstring(const char*txt);
/*
* Trace file for loggint ACC and TF calls.
* Trace file for logging ACC and TF calls.
*/
FILE* pli_trace;

2
libveriuser/veriusertfs.c
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@ -23,7 +23,7 @@
/*
* Contains the routines required to implement veriusertfs routines
* via VPI. This is extremly ugly, so don't look after eating dinner.
* via VPI. This is extremely ugly, so don't look after eating dinner.
*/
# include <string.h>

4
main.cc
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@ -85,7 +85,7 @@ const char*target = "null";
/*
* These are the language support control flags. These support which
* language features (the generation) to support. The generation_flag
* is a major moce, and the gn_* flags control specifc sub-features.
* is a major mode, and the gn_* flags control specific sub-features.
*/
generation_t generation_flag = GN_DEFAULT;
bool gn_cadence_types_flag = true;
@ -728,7 +728,7 @@ int main(int argc, char*argv[])
des->set_flags(flags);
/* Done iwth all the pform data. Delete the modules. */
/* Done with all the pform data. Delete the modules. */
for (map<perm_string,Module*>::iterator idx = pform_modules.begin()
; idx != pform_modules.end() ; idx ++) {

2
net_nex_input.cc
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@ -180,7 +180,7 @@ NexusSet* NetAssignBase::nex_input(bool rem_out)
{
NexusSet*result = rval_->nex_input(rem_out);
/* It is possible that the lval_ can hav nex_input values. In
/* It is possible that the lval_ can have nex_input values. In
particular, index expressions are statement inputs as well,
so should be addressed here. */
for (NetAssign_*cur = lval_ ; cur ; cur = cur->more) {

38
netlist.h
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@ -432,9 +432,9 @@ class NetDelaySrc : public NetObj {
/*
* NetNet is a special kind of NetObj that doesn't really do anything,
* but carries the properties of the wire/reg/trireg, including its
* name. Scalers and vectors are all the same thing here, a NetNet
* with a single pin. The difference between a scaler and vector is
* the video of the atomic vector datum it carries.
* name. Scalars and vectors are all the same thing here, a NetNet
* with a single pin. The difference between a scalar and vector is
* the width of the atomic vector datum it carries.
*
* NetNet objects can also appear as side effects of synthesis or
* other abstractions.
@ -504,7 +504,7 @@ class NetNet : public NetObj {
unsigned long vector_width() const;
/* This method converts a signed index (the type that might be
found in the verilog source) to a pin number. It accounts
found in the Verilog source) to a pin number. It accounts
for variation in the definition of the reg/wire/whatever. */
unsigned sb_to_idx(long sb) const;
@ -513,7 +513,7 @@ class NetNet : public NetObj {
the pin# from the index. */
bool sb_is_valid(long sb) const;
/* This method returns 0 for scalers and vectors, and greater
/* This method returns 0 for scalars and vectors, and greater
for arrays. The value is the number of array
indices. (Currently only one array index is supported.) */
unsigned array_dimensions() const;
@ -586,7 +586,7 @@ class NetAddSub : public NetNode {
~NetAddSub();
// Get the width of the device (that is, the width of the
// operands and results.)
// operands and results).
unsigned width() const;
Link& pin_Aclr();
@ -989,7 +989,7 @@ class NetMux : public NetNode {
* repeat count is a fixed value. This is just like the repeat
* concatenation of Verilog: {<repeat>{<vector>}}.
*
* When construction this node, the wid is the vector width of the
* When constructing this node, the wid is the vector width of the
* output, and the rpt is the repeat count. The wid must be an even
* multiple of the cnt, and wid/cnt is the expected input width.
*
@ -1519,7 +1519,7 @@ class NetUReduce : public NetNode {
/*
* The UDP is a User Defined Primitive from the Verilog source. Do not
* expand it out any further then this in the netlist, as this can be
* expand it out any further than this in the netlist, as this can be
* used to represent target device primitives.
*
* The UDP can be combinational or sequential. The sequential UDP
@ -1596,7 +1596,7 @@ class NetUDP : public NetNode {
/* =========
* A process is a behavioral-model description. A process is a
* statement that may be compound. the various statement types may
* statement that may be compound. The various statement types may
* refer to places in a netlist (by pointing to nodes) but is not
* linked into the netlist. However, elaborating a process may cause
* special nodes to be created to handle things like events.
@ -1607,7 +1607,7 @@ class NetProc : public virtual LineInfo {
explicit NetProc();
virtual ~NetProc();
// Find the Nexa that are input by the statement. This is used
// Find the nexa that are input by the statement. This is used
// for example by @* to find the inputs to the process for the
// sensitivity list.
virtual NexusSet* nex_input(bool rem_out = true);
@ -1632,7 +1632,7 @@ class NetProc : public virtual LineInfo {
// process. Most process types are not.
virtual bool is_synchronous();
// synthesize as asynchronous logic, and return true.
// Synthesize as asynchronous logic, and return true.
virtual bool synth_async(Design*des, NetScope*scope,
const NetBus&nex_map, NetBus&nex_out);
@ -1701,7 +1701,7 @@ class NetAssign_ {
void set_part(NetExpr* loff, unsigned wid);
// Get the width of the r-value that this node expects. This
// method accounts for the presence of the mux, so it not
// method accounts for the presence of the mux, so it is not
// necessarily the same as the pin_count().
unsigned lwidth() const;
@ -1858,7 +1858,7 @@ class NetBlock : public NetProc {
};
/*
* A CASE statement in the verilog source leads, eventually, to one of
* A CASE statement in the Verilog source leads, eventually, to one of
* these. This is different from a simple conditional because of the
* way the comparisons are performed. Also, it is likely that the
* target may be able to optimize differently.
@ -2040,7 +2040,7 @@ class NetDisable : public NetProc {
* block and starts the associated statement.
*
* The NetEvTrig class represents trigger statements. Executing this
* statement causes the referenced event to be triggered, which it
* statement causes the referenced event to be triggered, which in
* turn awakens the waiting threads. Each NetEvTrig object references
* exactly one event object.
*
@ -2583,8 +2583,8 @@ class NetProcTop : public LineInfo, public Attrib {
* p -- Arithmetic power (**)
* & -- Bit-wise AND
* | -- Bit-wise OR
* < -- Less then
* > -- Greater then
* < -- Less than
* > -- Greater than
* e -- Logical equality (==)
* E -- Case equality (===)
* L -- Less or equal
@ -2708,8 +2708,8 @@ class NetEBBits : public NetEBinary {
* this case the bit width of the expression is 1 bit, and the
* operands take their natural widths. The supported operators are:
*
* < -- Less then
* > -- Greater then
* < -- Less than
* > -- Greater than
* e -- Logical equality (==)
* E -- Case equality (===)
* L -- Less or equal (<=)
@ -2791,7 +2791,7 @@ class NetEBMult : public NetEBinary {
};
/*
* Support the binary multiplication (*) operator.
* Support the binary power (**) operator.
*/
class NetEBPow : public NetEBinary {

2
netmisc.h
View File

@ -89,7 +89,7 @@ extern NetNet*add_to_net(Design*des, NetNet*sig, long val);
* make_add_expr
* Make a NetEBAdd expression with <expr> the first argument and
* <val> the second. This may get turned into a subtract if <val> is
* less then zero. If val is exactly zero, then return <expr> as is.
* less than zero. If val is exactly zero, then return <expr> as is.
*
* make_sub_expr
* Make a NetEBAdd(subtract) node that subtracts the given

4
parse.y
View File

@ -1038,7 +1038,7 @@ expr_primary
delete $1;
}
/* An identifer followed by an expression list in parentheses is a
/* An identifier followed by an expression list in parentheses is a
function call. If a system identifier, then a system function
call. */
@ -1620,7 +1620,7 @@ module_port_list_opt
| { $$ = 0; }
;
/* Module declarations include optional ANSII style module parameter
/* Module declarations include optional ANSI style module parameter
ports. These are simply advance ways to declare parameters, so
that the port declarations may use them. */
module_parameter_port_list_opt

2
parse_api.h
View File

@ -33,7 +33,7 @@ class PUdp;
/*
* These are maps of the modules and primitives parsed from the
* Verilog source into pform for elaboration. The parser adds modules
* to these maps as it compiles modules in the verilog source.
* to these maps as it compiles modules in the Verilog source.
*/
extern map<perm_string,Module*> pform_modules;
extern map<perm_string,PUdp*> pform_primitives;

6
pform.cc
View File

@ -49,7 +49,7 @@ string vl_file = "";
extern int VLparse();
/* This tracks the current module being processed. There can only be
exactly one module currently being parsed, since verilog does not
exactly one module currently being parsed, since Verilog does not
allow nested module definitions. */
static Module*pform_cur_module = 0;
@ -1280,7 +1280,7 @@ void pform_module_define_port(const struct vlltype&li,
*/
/*
* this is the basic form of pform_makwire. This takes a single simple
* this is the basic form of pform_makewire. This takes a single simple
* name, port type, net type, data type, and attributes, and creates
* the variable/net. Other forms of pform_makewire ultimately call
* this one to create the wire and stash it.
@ -1295,7 +1295,7 @@ void pform_makewire(const vlltype&li, const char*nm,
PWire*cur = get_wire_in_module(name);
// If this is not implicit ("implicit" meaning we don't know
// what the type is yet) then set thay type now.
// what the type is yet) then set the type now.
if (cur && type != NetNet::IMPLICIT) {
bool rc = cur->set_wire_type(type);
if (rc == false) {

4
pform.h
View File

@ -40,7 +40,7 @@
/*
* These classes implement the parsed form (P-form for short) of the
* original verilog source. the parser generates the pform for the
* original Verilog source. the parser generates the pform for the
* convenience of later processing steps.
*/
@ -337,7 +337,7 @@ extern svector<PWire*>*pform_make_task_ports(NetNet::PortType pt,
/*
* These are functions that the outside-the-parser code uses the do
* interesting things to the verilog. The parse function reads and
* interesting things to the Verilog. The parse function reads and
* parses the source file and places all the modules it finds into the
* mod list. The dump function dumps a module to the output stream.
*/

2
target.h
View File

@ -153,7 +153,7 @@ struct expr_scan_t {
located in the target_table and used. */
extern int emit(const Design*des, const char*type);
/* This function takes a fully qualified verilog name (which may have,
/* This function takes a fully qualified Verilog name (which may have,
for example, dots in it) and produces a mangled version that can be
used by most any language. */
extern string mangle(const string&str);

2
tgt-stub/statement.c
View File

@ -124,7 +124,7 @@ static void show_stmt_release(ivl_statement_t net, unsigned ind)
}
/*
* A trigger statement is the "-> name;" syntax in verilog, where a
* A trigger statement is the "-> name;" syntax in Verilog, where a
* trigger signal is sent to a named event. The trigger statement is
* actually a very simple object.
*/

2
tgt-verilog/verilog.c
View File

@ -32,7 +32,7 @@
# include <stdio.h>
# include <assert.h>
/* This is the output file where the verilog program is sent. */
/* This is the output file where the Verilog program is sent. */
static FILE*out;
/*

2
tgt-vvp/vvp_priv.h
View File

@ -238,7 +238,7 @@ extern int draw_eval_real(ivl_expr_t ex);
/*
* draw_eval_bool64 evaluates a bool expression. The return code from
* the function is the index of the word register that contains the
* result. The word is allocated widh allocate_word(), so the caller
* result. The word is allocated with allocate_word(), so the caller
* must arrange for it to be released with clr_word(). The width must
* be such that it fits in a 64bit word.
*/

2
tgt-vvp/vvp_process.c
View File

@ -985,7 +985,7 @@ static int show_stmt_condit(ivl_statement_t net, ivl_scope_t sscope)
/*
* The delay statement is easy. Simply write a ``%delay <n>''
* instruction to delay the thread, then draw the included statement.
* The delay statement comes from verilog code like this:
* The delay statement comes from Verilog code like this:
*
* ...
* #<delay> <stmt>;

2
verinum.cc
View File

@ -532,7 +532,7 @@ ostream& operator<< (ostream&o, verinum::V v)
}
/*
* This operator is used by various dumpers to write the verilog
* This operator is used by various dumpers to write the Verilog
* number in a Verilog format.
*/
ostream& operator<< (ostream&o, const verinum&v)

2
vpi/sdf_parse_priv.h
View File

@ -32,7 +32,7 @@ struct port_with_edge_s {
/* Path to source for error messages. */
extern const char*sdf_parse_path;
/* Hierarchy seperator charactor to use. */
/* Hierarchy separator character to use. */
extern char sdf_use_hchar;
#endif

6
vpi/sys_display.c
View File

@ -190,7 +190,7 @@ static void format_time(unsigned mcd, int fsize,
/* This is the number of zeros I must add to the value to get
the desired precision within the fraction. If this value is
greater then 0, the value does not have enough characters,
greater than 0, the value does not have enough characters,
so I will be adding zeros. */
fraction_pad = time_units - format_precision;
@ -210,7 +210,7 @@ static void format_time(unsigned mcd, int fsize,
/* This is the number of zeros that I must add to the integer
part of the output string to pad the value out to the
desired units. This will only have a non-zero value if the
units of the value is greater then the desired units.
units of the value is greater than the desired units.
Detect the special case where the value is 0. In this case,
do not do any integer filling ever. The output should be
@ -1081,7 +1081,7 @@ static PLI_INT32 sys_monitor_calltf(PLI_BYTE8*name)
vpiHandle scope = vpi_handle(vpiScope, sys);
vpiHandle argv = vpi_iterate(vpiArgument, sys);
/* If there was a previous $monitor, then remove the calbacks
/* If there was a previous $monitor, then remove the callbacks
related to it. */
if (monitor_callbacks) {
for (idx = 0 ; idx < monitor_info.nitems ; idx += 1)

2
vpi/sys_finish.c
View File

@ -35,7 +35,7 @@ static PLI_INT32 sys_finish_compiletf(PLI_BYTE8 *name)
if (argv == 0) return 0;
arg = vpi_scan(argv);
/* A string diagnostic messege level makes no sense. */
/* A string diagnostic message level makes no sense. */
if (vpi_get(vpiType, arg) == vpiConstant &&
vpi_get(vpiConstType, arg) == vpiStringConst) {
vpi_printf("Error: %s does not take a string argument.\n", name);

2
vpi/sys_random.c
View File

@ -168,7 +168,7 @@ long rtl_dist_t(long *seed, long df)
return i;
}
/* copied from IEEE1364-2001, with slight midifications for 64bit machines. */
/* copied from IEEE1364-2001, with slight modifications for 64bit machines. */
long rtl_dist_uniform(long *seed, long start, long end)
{
double r;

2
vpi/sys_random_mti.c
View File

@ -146,7 +146,7 @@ static PLI_INT32 sys_mti_random_calltf(PLI_BYTE8*name)
context->mti = NP1;
assert(context);
/* squrrel away context */
/* squirrel away context */
vpi_put_userdata(call_handle, (void *)context);
}

6
vpi/sys_readmem.c
View File

@ -125,7 +125,7 @@ static PLI_INT32 sys_readmem_calltf(PLI_BYTE8*name)
int left_addr, right_addr;
/* start_addr and stop_addr are the parameters given to $readmem in the
verilog code. When not specified, start_addr is equal to the lower of
Verilog code. When not specified, start_addr is equal to the lower of
the [left,right]_addr and stop_addr is equal to the higher of the
[left,right]_addr. */
int start_addr, stop_addr, addr_incr;
@ -191,7 +191,7 @@ static PLI_INT32 sys_readmem_calltf(PLI_BYTE8*name)
return 0;
}
/* Check that ther is no 5th parameter */
/* Check that there is no 5th parameter */
if (vpi_scan(argv) != 0){
vpi_printf("ERROR: %s accepts maximum 4 parameters!\n", name );
vpi_free_object(argv);
@ -435,7 +435,7 @@ static PLI_INT32 sys_writemem_calltf(PLI_BYTE8*name)
return 0;
}
/* Check that ther is no 5th parameter */
/* Check that there is no 5th parameter */
if (vpi_scan(argv) != 0){
vpi_printf("ERROR: %s accepts maximum 4 parameters!\n", name );
vpi_free_object(argv);

4
vpip/vpi_const.c
View File

@ -253,10 +253,10 @@ void vpip_bits_get_value(const vpip_bit_t*bits, unsigned nbits,
break;
case vpiStringVal:
/* Turn the bits into an ascii string, terminated by a
/* Turn the bits into an ASCII string, terminated by a
null. This is actually a bit tricky as nulls in the
bit array would terminate the C string. I therefore
translate them to ascii ' ' characters. */
translate them to ASCII ' ' characters. */
assert(nbits%8 == 0);
for (idx = nbits ; idx >= 8 ; idx -= 8) {
char tmp = 0;

6
vpip/vpi_priv.h
View File

@ -222,9 +222,9 @@ extern struct __vpiNull *vpip_get_null(void);
/*
* This type represents the handle to a Verilog scope. These include
* module instantiations and name begin-end blocks. The attach
* module instantiations and named begin-end blocks. The attach
* function is used to attach handles to the scope by the runtime
* initializaiton.
* initialization.
*/
struct __vpiScope {
struct __vpiHandle base;
@ -380,7 +380,7 @@ extern void vpip_simulation_run();
extern void vpi_mcd_init(void);
/*
* Schedule an event to be run sometime in the future. The d parmater
* Schedule an event to be run sometime in the future. The d parameter
* is the delay in simulation units before the event is processed. If
* the non-block flag is set, the event is scheduled to happen at the
* end of the time step.

2
vpip/vpi_time.c
View File

@ -25,7 +25,7 @@
# include <stdio.h>
/*
* IEEE-1364 VPI pretty much mandates the existance of this sort of
* IEEE-1364 VPI pretty much mandates the existence of this sort of
* thing. (Either this or a huge memory leak.) Sorry.
*/
static char buf_obj[128];

2
vvp/array.cc
View File

@ -524,7 +524,7 @@ void compile_array_alias(char*label, char*name, char*src)
obj->name = vpip_name_string(name);
obj->array_count = mem->array_count;
// XXXX Need to set an accurate range of addreses.
// XXXX Need to set an accurate range of addresses.
vpip_make_dec_const(&obj->first_addr, mem->first_addr.value);
vpip_make_dec_const(&obj->last_addr, mem->last_addr.value);

2
vvp/delay.cc
View File

@ -195,7 +195,7 @@ void vvp_fun_delay::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit)
if (bit.size() < use_wid)
use_wid = bit.size();
/* Scan the vectors looking for delays. Select the maximim
/* Scan the vectors looking for delays. Select the maximum
delay encountered. */
vvp_time64_t use_delay;
use_delay = delay_.get_delay(cur_vec4_.value(0), bit.value(0));

4
vvp/delay.h
View File

@ -66,7 +66,7 @@ class vvp_delay_t {
* effort of calculating strength values either.
*
* The node needs a pointer to the vvp_net_t input so that it knows
* how to find its output when propaging delayed output.
* how to find its output when propagating delayed output.
*
* NOTE: This node supports vec4 and real by repeating whatever was
* input. This is a bit of a hack, as it may be more efficient to
@ -136,7 +136,7 @@ class vvp_fun_delay : public vvp_net_fun_t, private vvp_gen_event_s {
};
/*
* These objects inplement module delay paths. The fun_modpath functor
* These objects implement module delay paths. The fun_modpath functor
* is the output of the modpath, and the vvp_fun_modpath_src is the
* source of the modpath. The modpath source tracks events on the
* inputs to enable delays, and the vvp_fun_modpath, when it's time to

2
vvp/logic.h
View File

@ -131,7 +131,7 @@ class vvp_fun_bufz: public vvp_net_fun_t {
* The select input must be 1 bit wide. If it is 0, then the port-0
* vector is passed out. If select is 1, then port-1 is passed
* out. Otherwise, a vector is passed out that reflects x?: behavior
* in verilog. The width of the blended output is the width of the largest
* in Verilog. The width of the blended output is the width of the largest
* input (port-0 or port-1) to enter the device. The narrow vector is
* padded with X values.
*/

8
vvp/memory.h
View File

@ -75,9 +75,9 @@ extern void memory_set_word(vvp_memory_t mem,
vvp_vector4_t val);
/*
* this doesn't actually write the value to the memory word, but
* scedules for the write to happen some time in the future. The delay
* is in simulation clock units
* This doesn't actually write the value to the memory word, but
* schedules for the write to happen some time in the future. The delay
* is in simulation clock units.
*/
void schedule_memory(vvp_memory_t mem, unsigned addr,
vvp_vector4_t val, unsigned long delay);
@ -149,7 +149,7 @@ class vvp_fun_memport : public vvp_net_fun_t {
** The memory_find function locates the memory device by name. If the
** device does not exist, a nil is returned.
**
** The memory_create functio create a new memory device with the given
** The memory_create function creates a new memory device with the given
** name. It is a fatal error to try to create a device that already exists.
*/
vvp_memory_t memory_find(char *label);

4
vvp/npmos.cc
View File

@ -30,8 +30,8 @@ vvp_fun_pmos_::vvp_fun_pmos_(bool enable_invert)
void vvp_fun_pmos_::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
{
/* Data input is processed throught eh recv_vec8 method,
because the strength most be preserved. */
/* Data input is processed through eh recv_vec8 method,
because the strength must be preserved. */
if (ptr.port() == 0) {
vvp_vector8_t tmp = bit;
recv_vec8(ptr, tmp);

10
vvp/opcodes.txt
View File

@ -178,8 +178,8 @@ same, or 0 otherwise. The eq bit is true if the values are logically
the same. That is, x and z are considered equal. In other words the eq
bit is the same as ``=='' and the eeq bit ``===''.
The lt bit is 1 if the left vector is less then the right vector, or 0
if greater then or equal to the right vector. It is the equivalent of
The lt bit is 1 if the left vector is less than the right vector, or 0
if greater than or equal to the right vector. It is the equivalent of
the Verilog < operator. Combinations of these three bits can be used
to implement all the Verilog comparison operators.
@ -424,8 +424,8 @@ the specified thread register bit. The functor-label can refer to a
.net, a .var or a .functor with a vector output. The entire vector,
from the least significant up to <wid> bits, is loaded starting at
thread bit <bit>. It is an OK for the width to not match the vector
width at the functor. If the <wid> is less then the width at the
functor, the the most significant bits are dropped.
width at the functor. If the <wid> is less than the width at the
functor, then the most significant bits are dropped.
* %load/vp0 <bit>, <functor-label>, <wid>
@ -634,7 +634,7 @@ The addressing is canonical (0-based) so the compiler must figure out
non-zero offsets, if any. The width is the width of the part being
written. The other bits of the vector are not touched.
The index may be signed, and if less then 0, the beginning bits are
The index may be signed, and if less than 0, the beginning bits are
not assigned. Also, if the bits go beyond the end of the signal, those
bits are not written anywhere.

2
vvp/reduce.cc
View File

@ -33,7 +33,7 @@
/*
* All the reduction operations take a single vector input and produce
* a scalar result. The vvp_reduce_base class codifies these general
* charactoristics, leaving only the calculation of the result for the
* characteristics, leaving only the calculation of the result for the
* base class.
*/
class vvp_reduce_base : public vvp_net_fun_t {

2
vvp/resolv.h
View File

@ -26,7 +26,7 @@
# include "vvp_net.h"
/*
* This functor type resolves its inputs using the verilog method of
* This functor type resolves its inputs using the Verilog method of
* combining signals, and outputs that resolved value. The puller
* value is also blended with the result. This helps with the
* implementation of tri0 and tri1, which have pull constants

2
vvp/schedule.h
View File

@ -97,7 +97,7 @@ extern void schedule_init_vector(vvp_net_ptr_t ptr, double val);
* called.
*
* The sync_flag is true if this is intended to be a sync event. These
* are placed in the stratified event queue after nb assignes. If the
* are placed in the stratified event queue after nb assigns. If the
* ro_flag is true as well, then it is a Read-only sync event, with
* all that means.
*

4
vvp/udp.cc
View File

@ -101,7 +101,7 @@ vvp_udp_comb_s::~vvp_udp_comb_s()
* actual vector of inputs to be tested.
*
* The levels0_ and levels1_ tables have levels_table objects that
* eack represent a single row. For the row to match the input vector,
* each represent a single row. For the row to match the input vector,
* all the bits that are set in the cur table must also be set in the
* row being tested.
*
@ -677,7 +677,7 @@ vvp_bit4_t vvp_udp_seq_s::calculate_output(const udp_levels_table&cur,
* next output, or Z if there was no match. (This is different from
* the combinational version of this function, which returns X for the
* cases that don't match.) This method assumes that the caller has
* set the mask bit in bit postion [port_count()] to reflect the
* set the mask bit in bit position [port_count()] to reflect the
* current output.
*/
vvp_bit4_t vvp_udp_seq_s::test_levels_(const udp_levels_table&cur)

10
vvp/udp.h
View File

@ -60,7 +60,7 @@ struct vvp_udp_s {
*
* The ports argument of the constructor is the number of input ports
* to the device. The single output port is not counted. The port
* count must be greater then 0.
* count must be greater than 0.
*
* A level sensitive UDP has a table that includes all the rows that
* generate a 0 output and another table that includes all the rows
@ -141,9 +141,9 @@ class vvp_udp_comb_s : public vvp_udp_s {
* but one of the positions has an edge value.
*
* The port_count() for the device is the number of inputs. Sequential
* devices have and additional phantom port that is the current output
* value. This implies that the maximim port count for sequential
* devices is 1 less then for combinational.
* devices have an additional phantom port that is the current output
* value. This implies that the maximum port count for sequential
* devices is 1 less than for combinational.
*
* The input table that is passed to the compile_table method is very
* similar to that for the combinational UDP. The differences are that
@ -215,7 +215,7 @@ class vvp_udp_seq_s : public vvp_udp_s {
};
/*
* Ths looks up a UDP definition from its LABEL.
* This looks up a UDP definition from its LABEL.
*/
struct vvp_udp_s *udp_find(const char *label);

2
vvp/ufunc.h
View File

@ -39,7 +39,7 @@
*
* There are enough input functors to take all the function inputs, 4
* per functor. These inputs deliver the changed input value to the
* ufunc_core, which carries the infastructure for the thread. The
* ufunc_core, which carries the infrastructure for the thread. The
* ufunc_core is also a functor whose output is connected to the rest
* of the netlist. This is where the result is delivered back to the
* netlist.

2
vvp/vpi.txt
View File

@ -11,7 +11,7 @@ System tasks and functions in Verilog are implemented in Icarus
Verilog by C routines written with VPI. This implies that the vvp
engine must provide at least a subset of the Verilog VPI
interface. The minimalist concepts of vvp, however, make the method
less then obvious.
less than obvious.
Within a Verilog design, there is a more or less fixed web of
vpiHandles that is the design database as is available to VPI

4
vvp/vpi_mcd.cc
View File

@ -204,7 +204,7 @@ extern "C" PLI_INT32 vpi_mcd_flush(PLI_UINT32 mcd)
/*
* The vpi_fopen function opens a file with the given path, and
* returns a file descriptor that includes bit 31 set. This is to
* differentiate the fd from a mcd discriptor. Note that these
* differentiate the fd from a mcd descriptor. Note that these
* descriptors are distinct from the mcd descriptors, so uses a
* different fd table.
*/
@ -230,7 +230,7 @@ extern "C" FILE *vpi_get_file(PLI_INT32 fd)
// Only deal with FD's
if (IS_MCD(fd)) return NULL;
// Only know about FD_MAX indicies
// Only know about FD_MAX indices
if (FD_IDX(fd) >= FD_MAX) return NULL;
return fd_table[FD_IDX(fd)].fp;

2
vvp/vpi_modules.cc
View File

@ -78,7 +78,7 @@ void vpip_load_module(const char*name)
sprintf(buf, "%s.vpi", name);
rc = stat(buf, &sb);
/* Tray alwo with the .vpl suffix. */
/* Try also with the .vpl suffix. */
if (rc != 0) {
export_flag = true;
sprintf(buf, "%s.vpl", name);

2
vvp/vthread.txt
View File

@ -28,7 +28,7 @@ from the bit registers starting with the LSB and up.
The bit addresses 0, 1, 2 and 3 are special constant bits 0, 1, x and
z, and are used as read-only immediate values. If the instruction
takes a single bit operand, the the appropriate value is simply read
takes a single bit operand, then the appropriate value is simply read
out. If the instruction expects a vector, then a vector of the
expected width is created by replicating the constant value.

2
vvp/vvp_net.cc
View File

@ -1625,7 +1625,7 @@ vvp_fun_signal::vvp_fun_signal(unsigned wid, vvp_bit4_t init)
*
* NOTE: It is a quirk of vvp_fun_signal that it has an initial value
* that needs to be propagated, but after that it only needs to
* propagate if the value changes. Elimitating duplicate propagations
* propagate if the value changes. Eliminating duplicate propagations
* should improve performance, but has the quirk that an input that
* matches the initial value might not be propagated. The hack used
* herein is to keep a "needs_init_" flag that is turned false after

26
vvp/vvp_net.h
View File

@ -333,7 +333,7 @@ extern vvp_vector4_t c4string_to_vector4(const char*str);
extern ostream& operator<< (ostream&, const vvp_vector2_t&);
/*
* This class represents a scaler value with strength. These are
* This class represents a scalar value with strength. These are
* heavier then the simple vvp_bit4_t, but more information is
* carried by that weight.
*
@ -412,7 +412,7 @@ extern ostream& operator<< (ostream&, vvp_scalar_t);
* a well defined bit may have. When you add in ambiguous values, the
* number of distinct values span the vvp_scalar_t.
*
* a vvp_vector8_t object can be created from a vvp_vector4_t and a
* A vvp_vector8_t object can be created from a vvp_vector4_t and a
* strength value. The vvp_vector8_t bits have the values of the input
* vector, all with the strength specified. If no strength is
* specified, then the conversion from bit4 to a scalar will use the
@ -506,8 +506,8 @@ class vvp_net_ptr_t {
/*
* Alert! Ugly details. Protective clothing recommended!
* The vvp_net_ptr_t encodes the bits of a C pointer, and two bits of
* port identifer into an unsigned long. This works only if vvp_net_t*
* values are always aligned on 4byte boundaries.
* port identifier into an unsigned long. This works only if vvp_net_t*
* values are always aligned on 4-byte boundaries.
*/
inline vvp_net_ptr_t::vvp_net_ptr_t()
@ -688,8 +688,8 @@ class vvp_fun_repeat : public vvp_net_fun_t {
/* vvp_fun_drive
* This node function takes an input vvp_vector4_t as input, and
* repeats that value as a vvp_vector8_t with all the bits given the
* strength of the drive. This is the way vvp_scaler8_t objects are
* created. Input 0 is the value to be drived (vvp_vector4_t) and
* strength of the drive. This is the way vvp_scalar8_t objects are
* created. Input 0 is the value to be driven (vvp_vector4_t) and
* inputs 1 and two are the strength0 and strength1 values to use. The
* strengths may be taken as constant values, or adjusted as longs
* from the network.
@ -734,15 +734,15 @@ class vvp_fun_extend_signed : public vvp_net_fun_t {
* the type of its port-0 input. If vvp_vector4_t values come in
* through port-0, then vvp_vector4_t values are propagated. If
* vvp_vector8_t values come in through port-0, then vvp_vector8_t
* values are propaged. Thus, this node is sloghtly polymorphic.
* values are propagated. Thus, this node is slightly polymorphic.
*
* If the signal is a net (i.e. a wire or tri) then this node will
* have an input that is the data source. The data source will connect
* through port-0
* through port-0.
*
* If the signal is a reg, then there will be no netlist input, the
* values will be written by behavioral statements. The %set and
* %assign statements will write through port-0
* %assign statements will write through port-0.
*
* In any case, behavioral code is able to read the value that this
* node last propagated, by using the value() method. That is important
@ -778,7 +778,7 @@ class vvp_fun_extend_signed : public vvp_net_fun_t {
* 3 -- release/reg
* The release/reg command is similar to the release/net
* command, but the port-0 value is not propagated. Changes
* to port-0 (or port-1 if continuous assing is active) will
* to port-0 (or port-1 if continuous assign is active) will
* propagate starting at the next input change.
*/
@ -831,8 +831,8 @@ class vvp_fun_signal_base : public vvp_net_fun_t, public vvp_vpi_callback {
};
/*
* This abstract class is a little more specific the the signa_base
* class, in that in adds vector access methods.
* This abstract class is a little more specific than the signal_base
* class, in that it adds vector access methods.
*/
class vvp_fun_signal_vec : public vvp_fun_signal_base {
@ -939,7 +939,7 @@ class vvp_fun_signal_real : public vvp_fun_signal_base {
*
* There are enough input functors to take all the functor inputs, 4
* per functor. These inputs deliver the changed input value to the
* wide_fun_core, which carries the infastructure for the thread. The
* wide_fun_core, which carries the infrastructure for the thread. The
* wide_fun_core is also a functor whose output is connected to the rest
* of the netlist. This is where the result is delivered back to the
* netlist.