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Add regression tests for checking wire data types (issue 1087).

This commit is contained in:
Martin Whitaker 2024-01-28 15:53:47 +00:00
parent a8144fd249
commit 81d7abaf88
14 changed files with 68 additions and 0 deletions
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1
ivtest/gold/br_gh1087a1-iverilog-stderr.gold Normal file
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ivltests/br_gh1087a.v:3: Net data type requires SystemVerilog or -gxtypes.

2
ivtest/gold/br_gh1087a2-iverilog-stderr.gold Normal file
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ivltests/br_gh1087a.v:6: error: Unresolved net/uwire r cannot have multiple drivers.
1 error(s) during elaboration.

2
ivtest/gold/br_gh1087a3-iverilog-stderr.gold Normal file
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ivltests/br_gh1087a.v:3: error: Net `r` can not be of type `real`.
1 error(s) during elaboration.

2
ivtest/gold/br_gh1087b-iverilog-stderr.gold Normal file
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ivltests/br_gh1087b.v:6: error: Unresolved net/uwire b cannot have multiple drivers.
1 error(s) during elaboration.

2
ivtest/gold/br_gh1087c-iverilog-stderr.gold Normal file
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ivltests/br_gh1087c.v:3: error: Net `b` can not be of type `bool`.
1 error(s) during elaboration.

8
ivtest/ivltests/br_gh1087a.v Normal file
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module test();
wire real r;
assign r = 1.0;
assign r = 2.0;
endmodule

8
ivtest/ivltests/br_gh1087b.v Normal file
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module test();
wire bool [7:0] b;
assign b = 8'h11;
assign b = 8'h22;
endmodule

8
ivtest/ivltests/br_gh1087c.v Normal file
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module test();
wire bit [7:0] b;
assign b = 8'h11;
assign b = 8'h22;
endmodule

5
ivtest/regress-vvp.list
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@ -34,6 +34,11 @@ br_gh1018 vvp_tests/br_gh1018.json
br_gh1029 vvp_tests/br_gh1029.json
br_gh1075a vvp_tests/br_gh1074a.json
br_gh1075b vvp_tests/br_gh1074b.json
br_gh1087a1 vvp_tests/br_gh1087a1.json
br_gh1087a2 vvp_tests/br_gh1087a2.json
br_gh1087a3 vvp_tests/br_gh1087a3.json
br_gh1087b vvp_tests/br_gh1087b.json
br_gh1087c vvp_tests/br_gh1087c.json
ca_time_real` vvp_tests/ca_time_real.json
case1 vvp_tests/case1.json
case2 vvp_tests/case2.json

6
ivtest/vvp_tests/br_gh1087a1.json Normal file
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{
"type" : "CE",
"source" : "br_gh1087a.v",
"gold" : "br_gh1087a1",
"iverilog-args" : [ "-gno-xtypes" ]
}

6
ivtest/vvp_tests/br_gh1087a2.json Normal file
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@ -0,0 +1,6 @@
{
"type" : "CE",
"source" : "br_gh1087a.v",
"gold" : "br_gh1087a2",
"iverilog-args" : [ "-gxtypes" ]
}

6
ivtest/vvp_tests/br_gh1087a3.json Normal file
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@ -0,0 +1,6 @@
{
"type" : "CE",
"source" : "br_gh1087a.v",
"gold" : "br_gh1087a3",
"iverilog-args" : [ "-g2009", "-gno-xtypes" ]
}

6
ivtest/vvp_tests/br_gh1087b.json Normal file
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{
"type" : "CE",
"source" : "br_gh1087b.v",
"gold" : "br_gh1087b",
"iverilog-args" : [ "-gxtypes" ]
}

6
ivtest/vvp_tests/br_gh1087c.json Normal file
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@ -0,0 +1,6 @@
{
"type" : "CE",
"source" : "br_gh1087c.v",
"gold" : "br_gh1087c",
"iverilog-args" : [ "-g2009", "-gno-xtypes" ]
}