Handle proceedural writes to UWIRE objects.

The elaborator allows this only if it determines that the bits
that are procedural written are not also continuously written.

tgt-vvp/stmt_assign.c

@@ -453,8 +453,16 @@ static void set_vec_to_lval_slice(ivl_lval_t lval, unsigned bit, unsigned wid)
 	    assert(ivl_lval_width(lval) == wid);
 
 	      /* If the word index is a constant, then we can write
-	         directly to the word and save the index calculation. */
-	    if (word_ix == 0) {
+	         directly to the word and save the index
+	         calculation. Also, note the special case that we are
+	         writing to a UWIRE. In that case, use the %force/x0
+	         instruction to get the desired effect. */
+	    if (word_ix == 0 && ivl_signal_type(sig)==IVL_SIT_UWIRE) {
+		  fprintf(vvp_out, "    %%ix/load 0, %lu, 0;\n", part_off);
+		  fprintf(vvp_out, "    %%force/x0 v%p_%lu, %u, %u;\n",
+		          sig, use_word, bit, wid);
+
+	    } else if (word_ix == 0) {
 		  fprintf(vvp_out, "    %%ix/load 0, %lu, 0;\n", part_off);
 		  fprintf(vvp_out, "    %%set/x0 v%p_%lu, %u, %u;\n",
 		          sig, use_word, bit, wid);

vvp/vvp_net_sig.h

@@ -394,6 +394,16 @@ class vvp_fun_signal_object_aa : public vvp_fun_signal_object, public automatic_
  * The vvp_wire is different from vvp_variable objects in that it
  * exists only as a filter. The vvp_wire class tree is for
  * implementing verilog wires/nets (as opposed to regs/variables).
+ *
+ *   vvp_vpi_callback
+ *          |
+ *          |
+ *    vvp_net_fil_t   vvp_signal_value
+ *          |               |
+ *           \             /
+ *            \           /
+ *             \         /
+ *            vvp_wire_base
  */
 
 class vvp_wire_base  : public vvp_net_fil_t, public vvp_signal_value {