Add regression tests for non-ANSI integer module ports

Check that it is possible to declare the type separately from the direction
for non-ANSI integer, time and atom2 ports. Check that it is possible to
both declare the type before and after the direction.

For integer, time and atom2 types the range specification on the port
direction declaration should be empty, rather than the implicit packed
dimension of the integer type.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-03-16 09:10:52 +01:00
parent f6042033d0
commit 4c9af1c47a
9 changed files with 121 additions and 0 deletions

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@ -0,0 +1,24 @@
// Check that it is possible to declare the data type for an atom2 type module
// port separately from the direction for non-ANSI style port declarations.
// declarations.
module test(x, y, z, w);
output x;
output y;
output z;
output w;
byte x;
shortint y;
int z;
longint w;
initial begin
if ($bits(x) == 8 && $bits(y) == 16 &&
$bits(z) == 32 && $bits(w) == 64) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule

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@ -0,0 +1,23 @@
// Check that it is possible to declare the data type for an atom2 type module
// port before the direction for non-ANSI style port declarations.
module test(x, y, z, w);
byte x;
shortint y;
int z;
longint w;
output x;
output y;
output z;
output w;
initial begin
if ($bits(x) == 8 && $bits(y) == 16 &&
$bits(z) == 32 && $bits(w) == 64) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule

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@ -0,0 +1,17 @@
// Check that it is possible to declare the data type for an integer type module
// port separately from the direction for non-ANSI style port declarations.
// declarations.
module test(x);
output x;
integer x;
initial begin
if ($bits(x) == $bits(integer)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule

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@ -0,0 +1,16 @@
// Check that it is possible to declare the data type for an integer type module
// port before the direction for non-ANSI style port declarations.
module test(x);
integer x;
output x;
initial begin
if ($bits(x) == $bits(integer)) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule

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@ -0,0 +1,17 @@
// Check that it is possible to declare the data type for a time type module
// port separately from the direction for non-ANSI style port declarations.
// declarations.
module test(x);
output x;
time x;
initial begin
if ($bits(x) == 64) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule

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@ -0,0 +1,16 @@
// Check that it is possible to declare the data type for a time type module
// port before the direction for non-ANSI style port declarations.
module test(x);
time x;
output x;
initial begin
if ($bits(x) == 64) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule

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@ -338,6 +338,8 @@ logp2 normal,-g2005-sv ivltests
mod_inst_pkg normal,-g2009 ivltests
module_nonansi_enum1 normal,-g2005-sv ivltests
module_nonansi_enum2 normal,-g2005-sv ivltests
module_nonansi_int1 normal,-g2005-sv ivltests
module_nonansi_int2 normal,-g2005-sv ivltests
module_nonansi_parray1 normal,-g2005-sv ivltests
module_nonansi_parray2 normal,-g2005-sv ivltests
module_nonansi_real1 normal,-g2005-sv ivltests

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@ -650,6 +650,10 @@ module3.12A normal ivltests main
module3.12B normal ivltests
module_inout_port_type CE ivltests
module_input_port_type CE ivltests
module_nonansi_integer1 normal ivltests
module_nonansi_integer2 normal ivltests
module_nonansi_time1 normal ivltests
module_nonansi_time2 normal ivltests
module_nonansi_vec1 normal ivltests
module_nonansi_vec2 normal ivltests
module_output_port_var1 normal ivltests

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@ -796,6 +796,8 @@ iuint1 normal,-g2009,-pallowsigned=1 ivltests
logp2 normal,-g2009,-pallowsigned=1 ivltests
mixed_width_case normal,-pallowsigned=1 ivltests
mod_inst_pkg normal,-g2009,-pallowsigned=1 ivltests
module_nonansi_int1 normal,-g2005-sv,-pallowsigned=1 ivltests
module_nonansi_int2 normal,-g2005-sv,-pallowsigned=1 ivltests
module_output_port_sv_var1 normal,-g2005-sv,-pallowsigned=1 ivltests
module_output_port_sv_var2 normal,-g2005-sv,-pallowsigned=1 ivltests
module_output_port_var1 normal,-pallowsigned=1 ivltests