luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Insert blank line before VHDL process in output

This commit is contained in:
Nick Gasson 2008-08-02 10:45:38 +01:00
parent a60216ec15
commit 752a90dc2f
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tgt-vhdl/vhdl_syntax.cc
View File

@ -166,7 +166,8 @@ void vhdl_process::emit(std::ostream &of, int level) const
newline(of, level);
return;
}
newline(of, level);
emit_comment(of, level);
if (name_.size() > 0)
of << name_ << ": ";
@ -189,7 +190,6 @@ void vhdl_process::emit(std::ostream &of, int level) const
of << "begin";
stmts_.emit(of, level);
of << "end process;";
newline(of, level);
}
stmt_container::~stmt_container()