luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

improved test

This commit is contained in:
Ethan Sifferman 2023-07-29 00:21:31 -07:00
parent 44badf50de
commit de2f506644
1 changed files with 36 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
ivtest/ivltests/sv_argumentless_func.v
View File

@ -2,23 +2,50 @@
module test;
function automatic [7:0] test_func;
input _unused;
test_func = _unused;
test_func = 8'h1;
endfunction
logic [7:0] test_assign;
assign test_assign = test_func(0);
logic [7:0] test_alwayscomb;
always_comb test_alwayscomb = test_func();
wire [7:0] test_wire = test_func(0);
logic [7:0] test_alwaysff;
logic clk;
always_ff @(posedge clk) test_alwaysff <= test_func();
logic [7:0] test_assign;
assign test_assign = test_func();
wire [7:0] test_wire = test_func();
initial begin
if (test_assign !== test_func(0)) begin
$display("FAILED -- test_assign=%h, expect %h", test_assign, test_func(0));
#1;
if (test_func() !== 8'h1) begin
$display("FAILED -- test_func()=%h, expect %h", test_func(), 8'h1);
$finish;
end
if (test_wire !== test_func(0)) begin
$display("FAILED -- test_wire=%h, expect %h", test_wire, test_func(0));
if (test_alwayscomb !== test_func()) begin
$display("FAILED -- test_alwayscomb=%h, expect %h", test_alwayscomb, test_func());
$finish;
end
if (test_assign !== test_func()) begin
$display("FAILED -- test_assign=%h, expect %h", test_assign, test_func());
$finish;
end
if (test_wire !== test_func()) begin
$display("FAILED -- test_wire=%h, expect %h", test_wire, test_func());
$finish;
end
clk = 0;
#1;
clk = 1;
#1;
if (test_alwaysff !== test_func()) begin
$display("FAILED -- test_alwaysff=%h, expect %h", test_alwaysff, test_func());
$finish;
end