Generate VHDL report statements for $display
This changes the implementation of $display/$write to use VHDL report statements rather the the std.textio functions. The code produced is simpler and more like what a real VHDL designed would write. However it no longer exactly matches the Verilog output as most VHDL simulators prepend the text with simulation time, entity name, severity level, etc. There is a corresponding change in ivtest to support this.
This commit is contained in:
Nick Gasson
parent
0cec4495ca
commit
48ae8c1ce5
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@ -50,7 +50,7 @@ dep:
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mv $*.d dep
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O = vhdl.o state.o vhdl_element.o vhdl_type.o vhdl_syntax.o scope.o process.o \
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stmt.o expr.o lpm.o display.o support.o cast.o logic.o
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stmt.o expr.o lpm.o support.o cast.o logic.o
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ifeq (@WIN32@,yes)
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TGTLDFLAGS=-L.. -livl
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@ -56,6 +56,8 @@ vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
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return to_vector(to->get_name(), to->get_width());
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case VHDL_TYPE_STD_LOGIC:
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return to_std_logic();
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case VHDL_TYPE_STRING:
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return to_string();
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default:
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assert(false);
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}
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@ -112,6 +114,25 @@ vhdl_expr *vhdl_expr::to_integer()
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return conv;
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}
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vhdl_expr *vhdl_expr::to_string()
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{
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bool numeric = type_->get_name() == VHDL_TYPE_UNSIGNED
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|| type_->get_name() == VHDL_TYPE_SIGNED;
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if (numeric) {
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vhdl_fcall *image = new vhdl_fcall("integer'image", vhdl_type::string());
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image->add_expr(this->cast(vhdl_type::integer()));
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return image;
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}
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else {
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// Assume type'image exists
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vhdl_fcall *image = new vhdl_fcall(type_->get_string() + "'image",
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vhdl_type::string());
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image->add_expr(this);
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return image;
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}
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}
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/*
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* Convert a generic expression to a Boolean.
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*/
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@ -1,200 +0,0 @@
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/*
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* VHDL implementation of $display.
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*
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* Copyright (C) 2008-2009 Nick Gasson (nick@nickg.me.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "vhdl_target.h"
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#include <iostream>
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#include <cstring>
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#include <cassert>
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#include <cctype>
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#include <sstream>
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static const char *DISPLAY_LINE = "Verilog_Display_Line";
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/*
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* Write a VHDL expression into the current display line.
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*/
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static void display_write(stmt_container *container, vhdl_expr *expr)
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{
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vhdl_pcall_stmt *write = new vhdl_pcall_stmt("Write");
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vhdl_var_ref *ref =
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new vhdl_var_ref(DISPLAY_LINE, vhdl_type::line());
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write->add_expr(ref);
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vhdl_type_name_t type = expr->get_type()->get_name();
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if (type == VHDL_TYPE_SIGNED || type == VHDL_TYPE_UNSIGNED) {
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vhdl_type integer(VHDL_TYPE_INTEGER);
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write->add_expr(expr->cast(&integer));
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}
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else if (type != VHDL_TYPE_STRING) {
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// Need to add a call to Type'Image for types not
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// supported by std.textio
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std::string name(expr->get_type()->get_string());
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name += "'Image";
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vhdl_fcall *cast
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= new vhdl_fcall(name.c_str(), vhdl_type::string());
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cast->add_expr(expr);
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write->add_expr(cast);
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}
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else
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write->add_expr(expr);
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container->add_stmt(write);
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}
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/*
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* Write the value of DISPLAY_LINE to the output.
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*/
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static void display_line(stmt_container *container)
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{
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vhdl_pcall_stmt *write_line = new vhdl_pcall_stmt("WriteLine");
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vhdl_var_ref *output_ref =
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new vhdl_var_ref("std.textio.Output", new vhdl_type(VHDL_TYPE_FILE));
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write_line->add_expr(output_ref);
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vhdl_var_ref *ref =
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new vhdl_var_ref(DISPLAY_LINE, vhdl_type::line());
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write_line->add_expr(ref);
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container->add_stmt(write_line);
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}
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/*
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* Parse an octal escape sequence.
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*/
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static char parse_octal(const char *p)
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{
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assert(*p && *(p+1) && *(p+2));
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assert(isdigit(*p) && isdigit(*(p+1)) && isdigit(*(p+1)));
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return (*p - '0') * 64
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+ (*(p+1) - '0') * 8
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+ (*(p+2) - '0') * 1;
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}
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static void flush_string(std::ostringstream &ss, stmt_container *container)
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{
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display_write(container, new vhdl_const_string(ss.str().c_str()));
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// Clear the stream
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ss.str("");
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}
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// This should display the hierarchical module name, but we don't support
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// this in VHDL. So just emit a warning.
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static void display_m(stmt_container* container)
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{
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cerr << "Warning: no VHDL translation for %m format code" << endl;
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}
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/*
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* Generate VHDL for the $display system task.
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* This is implemented using the functions in std.textio. Each
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* parameter is written to a line variable in the process and
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* then the line is written to the special variable `Output'
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* (which represents the console). Subsequent $displays will
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* use the same line variable.
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*
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* It's possible, although quite unlikely, that there will be
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* name collision with an existing variable called
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* `Verilog_Display_Line' -- do something about this?
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*/
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int draw_stask_display(vhdl_procedural *proc, stmt_container *container,
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ivl_statement_t stmt, bool newline)
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{
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if (!proc->get_scope()->have_declared(DISPLAY_LINE)) {
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vhdl_var_decl *line_var =
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new vhdl_var_decl(DISPLAY_LINE, vhdl_type::line());
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line_var->set_comment("For generating $display output");
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proc->get_scope()->add_decl(line_var);
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}
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// Write the data into the line
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int count = ivl_stmt_parm_count(stmt), i = 0;
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while (i < count) {
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// $display may have an empty parameter, in which case
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// the expression will be null
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// The behaviour here seems to be to output a space
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ivl_expr_t net = ivl_stmt_parm(stmt, i++);
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if (net == NULL) {
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display_write(container, new vhdl_const_string(" "));
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continue;
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}
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if (ivl_expr_type(net) == IVL_EX_STRING) {
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ostringstream ss;
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for (const char *p = ivl_expr_string(net); *p; p++) {
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if (*p == '\\') {
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// Octal escape
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char ch = parse_octal(p+1);
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if (ch == '\n') {
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flush_string(ss, container);
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display_line(container);
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}
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else
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ss << ch;
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p += 3;
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}
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else if (*p == '%' && *(++p) != '%') {
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flush_string(ss, container);
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// Skip over width for now
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while (isdigit(*p)) ++p;
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switch (*p) {
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case 'm':
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display_m(container);
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break;
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default:
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{
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assert(i < count);
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ivl_expr_t netp = ivl_stmt_parm(stmt, i++);
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assert(netp);
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vhdl_expr *base = translate_expr(netp);
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if (NULL == base)
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return 1;
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display_write(container, base);
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}
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}
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}
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else
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ss << *p;
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}
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// Call Write on any non-empty string data left in the buffer
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if (!ss.str().empty())
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display_write(container, new vhdl_const_string(ss.str().c_str()));
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}
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else {
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vhdl_expr *base = translate_expr(net);
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if (NULL == base)
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return 1;
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display_write(container, base);
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}
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}
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if (newline)
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display_line(container);
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return 0;
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}
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107
tgt-vhdl/stmt.cc
107
tgt-vhdl/stmt.cc
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@ -30,6 +30,9 @@
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#include <set>
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#include <algorithm>
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static void emit_wait_for_0(vhdl_procedural *proc, stmt_container *container,
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ivl_statement_t stmt, vhdl_expr *expr);
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/*
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* VHDL has no real equivalent of Verilog's $finish task. The
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* current solution is to use `assert false ...' to terminate
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@ -57,6 +60,106 @@ static int draw_stask_finish(vhdl_procedural *proc, stmt_container *container,
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return 0;
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}
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static char parse_octal(const char *p)
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{
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assert(*p && *(p+1) && *(p+2));
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assert(isdigit(*p) && isdigit(*(p+1)) && isdigit(*(p+1)));
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return (*p - '0') * 64
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+ (*(p+1) - '0') * 8
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+ (*(p+2) - '0') * 1;
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}
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// Generate VHDL report statements for Verilog $display/$write
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static int draw_stask_display(vhdl_procedural *proc,
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stmt_container *container,
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ivl_statement_t stmt)
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{
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vhdl_binop_expr *text = new vhdl_binop_expr(VHDL_BINOP_CONCAT,
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vhdl_type::string());
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const int count = ivl_stmt_parm_count(stmt);
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int i = 0;
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while (i < count) {
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// $display may have an empty parameter, in which case
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// the expression will be null
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// The behaviour here seems to be to output a space
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ivl_expr_t net = ivl_stmt_parm(stmt, i++);
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if (net == NULL) {
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text->add_expr(new vhdl_const_string(" "));
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continue;
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}
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if (ivl_expr_type(net) == IVL_EX_STRING) {
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ostringstream ss;
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for (const char *p = ivl_expr_string(net); *p; p++) {
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if (*p == '\\') {
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// Octal escape
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char ch = parse_octal(p+1);
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if (ch == '\n') {
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// Is there a better way of handling newlines?
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// Maybe generate another report statement
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}
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else
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ss << ch;
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p += 3;
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}
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else if (*p == '%' && *(++p) != '%') {
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// Flush the output string up to this point
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text->add_expr(new vhdl_const_string(ss.str()));
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ss.str("");
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// Skip over width for now
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while (isdigit(*p)) ++p;
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switch (*p) {
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case 'm':
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// TOOD: we can get the module name via attributes
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cerr << "Warning: no VHDL translation for %m format code"
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<< endl;
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break;
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default:
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{
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assert(i < count);
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ivl_expr_t netp = ivl_stmt_parm(stmt, i++);
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assert(netp);
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vhdl_expr *base = translate_expr(netp);
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if (NULL == base)
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return 1;
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emit_wait_for_0(proc, container, stmt, base);
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text->add_expr(base->cast(text->get_type()));
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}
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}
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}
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else
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ss << *p;
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}
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// Emit any non-empty string data left in the buffer
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if (!ss.str().empty())
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text->add_expr(new vhdl_const_string(ss.str()));
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}
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else {
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vhdl_expr *base = translate_expr(net);
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if (NULL == base)
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return 1;
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emit_wait_for_0(proc, container, stmt, base);
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text->add_expr(base->cast(text->get_type()));
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}
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}
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if (count == 0)
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text->add_expr(new vhdl_const_string(""));
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container->add_stmt(new vhdl_report_stmt(text));
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return 0;
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}
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/*
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* Generate VHDL for system tasks (like $display). Not all of
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* these are supported.
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@ -67,9 +170,9 @@ static int draw_stask(vhdl_procedural *proc, stmt_container *container,
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const char *name = ivl_stmt_name(stmt);
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if (strcmp(name, "$display") == 0)
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return draw_stask_display(proc, container, stmt, true);
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return draw_stask_display(proc, container, stmt);
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else if (strcmp(name, "$write") == 0)
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return draw_stask_display(proc, container, stmt, false);
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return draw_stask_display(proc, container, stmt);
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else if (strcmp(name, "$finish") == 0)
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return draw_stask_finish(proc, container, stmt);
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else {
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@ -135,7 +135,6 @@ void vhdl_entity::emit(std::ostream &of, int level) const
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of << "library ieee;" << std::endl;
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of << "use ieee.std_logic_1164.all;" << std::endl;
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of << "use ieee.numeric_std.all;" << std::endl;
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of << "use std.textio.all;" << std::endl;
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of << std::endl;
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emit_comment(of, level);
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@ -620,11 +619,7 @@ void vhdl_var_ref::emit(std::ostream &of, int level) const
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void vhdl_const_string::emit(std::ostream &of, int level) const
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{
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// In some instances a string literal can be ambiguous between
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// a String type and some other types (e.g. std_logic_vector)
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// The explicit cast to String removes this ambiguity (although
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// isn't always strictly necessary)
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of << "String'(\"" << value_ << "\")";
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of << "\"" << value_ << "\"";
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}
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void vhdl_null_stmt::emit(std::ostream &of, int level) const
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@ -51,6 +51,7 @@ public:
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virtual vhdl_expr *to_integer();
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virtual vhdl_expr *to_std_logic();
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virtual vhdl_expr *to_vector(vhdl_type_name_t name, int w);
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virtual vhdl_expr *to_string();
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virtual void find_vars(vhdl_var_set_t& read) {}
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protected:
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@ -175,7 +176,7 @@ private:
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class vhdl_const_string : public vhdl_expr {
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public:
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vhdl_const_string(const char *value)
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vhdl_const_string(const string& value)
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: vhdl_expr(vhdl_type::string(), true), value_(value) {}
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void emit(std::ostream &of, int level) const;
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@ -268,7 +269,7 @@ private:
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*/
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class vhdl_fcall : public vhdl_expr {
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public:
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vhdl_fcall(const char *name, vhdl_type *rtype)
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vhdl_fcall(const string& name, vhdl_type *rtype)
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: vhdl_expr(rtype), name_(name) {};
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~vhdl_fcall() {}
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@ -1,3 +1,4 @@
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// -*- mode: c++ -*-
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#ifndef INC_VHDL_TARGET_H
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#define INC_VHDL_TARGET_H
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@ -29,8 +30,6 @@ vhdl_var_ref *nexus_to_var_ref(vhdl_scope *arch_scope, ivl_nexus_t nexus);
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vhdl_var_ref* readable_ref(vhdl_scope* scope, ivl_nexus_t nex);
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string make_safe_name(ivl_signal_t sig);
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int draw_stask_display(vhdl_procedural *proc, stmt_container *container,
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ivl_statement_t stmt, bool newline = true);
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void require_support_function(support_function_t f);
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#endif /* #ifndef INC_VHDL_TARGET_H */
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