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Explicit 'reg' return type in function definition 

Verilog allows returning variables of 'reg' type. The icarus verilog
implicitly assumes the default returned type of the function as
'reg unsigned'. The patch allows to explicitly specify the 'reg' return
type.

Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
This commit is contained in:
Prasad Joshi 2011-06-29 13:40:04 +01:00 committed by Stephen Williams
parent d07db53f0e
commit e497c1f1dc
1 changed files with 10 additions and 0 deletions
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@ -3509,6 +3509,16 @@ function_range_or_type_opt
: range { $$.range = make_range_vector($1); $$.type = PTF_REG; }
| K_signed range { $$.range = make_range_vector($2); $$.type = PTF_REG_S; }
| K_unsigned range { $$.range = make_range_vector($2); $$.type = PTF_REG; }
| K_reg unsigned_signed_opt range_opt
{
/* the default type is reg unsigned and no range */
$$.type = PTF_REG;
$$.range = 0;
if ($2)
$$.type = PTF_REG_S;
if ($3)
$$.range = make_range_vector($3);
}
| K_integer { $$.range = 0; $$.type = PTF_INTEGER; }
| K_real { $$.range = 0; $$.type = PTF_REAL; }
| K_realtime { $$.range = 0; $$.type = PTF_REALTIME; }