Initialization of atom types in module declaration

The module declaration should allow initialization of atom types (byte,
short int, int, and longint) data types.

For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output byte p = '1);
initial begin
	#200;
	$display("p = %b", p);
	$finish;
end

initial forever #10 clk = ~clk;
endmodule

$ iverilog -g 2009 clkgen.sv

$ ./a.out
p = 11111111

$

Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
This commit is contained in:
Prasad Joshi 2011-07-11 18:15:39 +01:00 committed by Stephen Williams
parent f0ffac6038
commit 743cb234c0
1 changed files with 22 additions and 0 deletions

22
parse.y
View File

@ -2251,6 +2251,28 @@ port_declaration
delete[]$5;
$$ = ptmp;
}
| attribute_list_opt K_output atom2_type signed_unsigned_opt IDENTIFIER '=' expression
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($5);
list<PExpr*>*use_range = make_range_from_width($3);
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
NetNet::IMPLICIT_REG, IVL_VT_BOOL,
$4, use_range, $1);
port_declaration_context.port_type = NetNet::POUTPUT;
port_declaration_context.port_net_type = NetNet::IMPLICIT_REG;
port_declaration_context.var_type = IVL_VT_BOOL;
port_declaration_context.sign_flag = $4;
delete port_declaration_context.range;
port_declaration_context.range = use_range;
pform_make_reginit(@5, name, $7);
delete[]$5;
$$ = ptmp;
}
;