luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix for br946 - procedural continuous assignment causes vvp internal error. 

In the case that the RHS of a procedural continuous assignment is a simple
vector that is wider than the LHS, changes to the RHS vector cause the
entire vector to be sent to port 1 of the LHS vvp_fun_signal object. This
vector needs to be coerced to the size of the LHS. Note that this is a
stopgap fix until vvp handles arbitrary expressions on the RHS of a
procedural continuous assignment.
This commit is contained in:
Martin Whitaker 2014-02-21 22:48:50 +00:00
parent 345c9cf21c
commit a76be3571d
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
vvp/vvp_net_sig.cc
View File

@ -200,7 +200,11 @@ void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
break;
case 1: // Continuous assign value
bits4_ = bit;
// Handle the simple case of the linked source being wider
// than this signal. Note we don't yet support the case of
// the linked source being narrower than this signal, or
// the case of an expression being assigned.
bits4_ = coerce_to_width(bit, bits4_.size());
assign_mask_ = vvp_vector2_t(vvp_vector2_t::FILL1, bits4_.size());
ptr.ptr()->send_vec4(bits4_, 0);
break;