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Change indentation mechanism in debug dump for VHDL 

There has been added additional default attribute to
all 'dump' function calls which is in all cases equal
to 0. Now one can specify how much this debug dumping should
be intended. This should allow people to dump smoothly whole
designs (as it was now) as far as separate units.

This is now the parent who specifies the base indentation
for all components (children). For example, architecture
"decides" how much their signals should be indented.
This commit is contained in:
Pawel Szostek 2011-04-06 17:27:58 +02:00 committed by Stephen Williams
parent 298495be97
commit 240880d81b
5 changed files with 44 additions and 44 deletions
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8
vhdlpp/architec.h
View File

@ -48,7 +48,7 @@ class Architecture : public LineInfo {
virtual ~Statement() =0;
virtual int emit(ostream&out, Entity*ent, Architecture*arc);
virtual void dump(ostream&out) const;
virtual void dump(ostream&out, int indent = 0) const;
private:
@ -75,7 +75,7 @@ class Architecture : public LineInfo {
int emit(ostream&out, Entity*entity);
// The dump method writes a debug display to the given output.
void dump(ostream&out, perm_string of_entity) const;
void dump(ostream&out, perm_string of_entity, int indent = 0) const;
private:
perm_string name_;
@ -100,7 +100,7 @@ class SignalAssignment : public Architecture::Statement {
~SignalAssignment();
int emit(ostream&out, Entity*entity, Architecture*arc);
virtual void dump(ostream&out) const;
virtual void dump(ostream&out, int indent = 0) const;
private:
ExpName*lval_;
@ -115,7 +115,7 @@ class ComponentInstantiation : public Architecture::Statement {
~ComponentInstantiation();
int emit(ostream&out, Entity*entity, Architecture*arc);
virtual void dump(ostream&out) const;
virtual void dump(ostream&out, int indent = 0) const;
private:
perm_string iname_;

56
vhdlpp/debug.cc
View File

@ -55,16 +55,16 @@ void dump_design_entities(const char*path)
}
}
void ComponentBase::dump_ports(ostream&out) const
void ComponentBase::dump_ports(ostream&out, int indent) const
{
if (ports_.size() == 0) {
out << " No ports" << endl;
out << setw(indent) << "" << "No ports" << endl;
} else {
out << " PORTS:" << endl;
out << setw(indent) << "" << "PORTS:" << endl;
for (vector<InterfacePort*>::const_iterator cur = ports_.begin()
; cur != ports_.end() ; ++cur) {
InterfacePort*item = *cur;
out << setw(6) << "" << item->name
out << setw(indent+2) << "" << item->name
<< " : " << item->mode
<< ", type=";
if (item->type)
@ -76,74 +76,74 @@ void ComponentBase::dump_ports(ostream&out) const
}
}
void Entity::dump(ostream&out) const
void Entity::dump(ostream&out, int indent) const
{
out << "entity " << get_name()
out << setw(indent) << "" << "entity " << get_name()
<< " file=" << get_fileline() << endl;
dump_ports(out);
dump_ports(out, indent+2);
for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin()
; cur != arch_.end() ; ++cur) {
cur->second->dump(out, get_name());
cur->second->dump(out, get_name(), indent);
}
}
void Architecture::dump(ostream&out, perm_string of_entity) const
void Architecture::dump(ostream&out, perm_string of_entity, int indent) const
{
out << "architecture " << name_
out << setw(indent) << "" << "architecture " << name_
<< " of entity " << of_entity
<< " file=" << get_fileline() << endl;
// Dump signal declarations
for (map<perm_string,Signal*>::const_iterator cur = signals_.begin()
; cur != signals_.end() ; ++cur) {
cur->second->dump(out);
cur->second->dump(out, indent+3);
}
// Dump component declarations
for (map<perm_string,ComponentBase*>::const_iterator cur = components_.begin()
; cur != components_.end() ; ++cur) {
out << " component " << cur->first << " is" << endl;
cur->second->dump_ports(out);
out << " end component " << cur->first << endl;
out << setw(indent+3) << "" << "component " << cur->first << " is" << endl;
cur->second->dump_ports(out, 3);
out << setw(indent+3) << "" << "end component " << cur->first << endl;
}
for (list<Architecture::Statement*>::const_iterator cur = statements_.begin()
; cur != statements_.end() ; ++cur) {
(*cur)->dump(out);
(*cur)->dump(out, indent+3);
}
}
void Architecture::Statement::dump(ostream&out) const
void Architecture::Statement::dump(ostream&out, int indent) const
{
out << " Architecture::Statement at file=" << get_fileline() << endl;
out << setw(indent) << "" << "Architecture::Statement at file=" << get_fileline() << endl;
}
void Signal::dump(ostream&out) const
void Signal::dump(ostream&out, int indent) const
{
out << " signal " << name_ << " is " << *type_ << endl;
out << setw(indent) << "" << "signal " << name_ << " is " << *type_ << endl;
}
void SignalAssignment::dump(ostream&out) const
void SignalAssignment::dump(ostream&out, int indent) const
{
out << " SignalAssignment file=" << get_fileline() << endl;
lval_->dump(out, 4);
out << " <= <expr>..." << endl;
out << setw(indent) << "" << "SignalAssignment file=" << get_fileline() << endl;
lval_->dump(out, indent+1);
out << setw(indent+2) << "" << "<= <expr>..." << endl;
for (list<Expression*>::const_iterator cur = rval_.begin()
; cur != rval_.end() ; ++cur) {
(*cur)->dump(out, 5);
(*cur)->dump(out, indent+2);
}
}
void ComponentInstantiation::dump(ostream&out) const
void ComponentInstantiation::dump(ostream&out, int indent) const
{
out << " Component Instantiation file=" << get_fileline() << endl;
out << setw(indent) << "" << "Component Instantiation file=" << get_fileline() << endl;
for (map<perm_string,Expression*>::const_iterator cur = port_map_.begin()
; cur != port_map_.end() ; ++cur) {
out << " " << cur->first << " => ..." << endl;
cur->second->dump(out, 10);
out << setw(indent+2) <<""<< cur->first << " => ..." << endl;
cur->second->dump(out, indent+6);
}
}

4
vhdlpp/entity.h
View File

@ -62,7 +62,7 @@ class ComponentBase : public LineInfo {
void set_interface(std::list<InterfacePort*>*ports);
public:
void dump_ports(ostream&out) const;
void dump_ports(ostream&out, int indent = 0) const;
protected:
// This is really only used by the Entity derived class.
@ -93,7 +93,7 @@ class Entity : public ComponentBase {
int elaborate();
int emit(ostream&out);
void dump(ostream&out) const;
void dump(ostream&out, int indent = 0) const;
private:
std::map<perm_string,Architecture*>arch_;

18
vhdlpp/expression.h
View File

@ -56,7 +56,7 @@ class Expression : public LineInfo {
virtual bool is_primary(void) const;
// Debug dump of the expression.
virtual void dump(ostream&out, int indent) const =0;
virtual void dump(ostream&out, int indent = 0) const =0;
private:
@ -73,7 +73,7 @@ class ExpUnary : public Expression {
protected:
int emit_operand1(ostream&out, Entity*ent, Architecture*arc);
void dump_operand1(ostream&out, int indent) const;
void dump_operand1(ostream&out, int indent = 0) const;
private:
Expression*operand1_;
@ -94,7 +94,7 @@ class ExpBinary : public Expression {
int emit_operand1(ostream&out, Entity*ent, Architecture*arc);
int emit_operand2(ostream&out, Entity*ent, Architecture*arc);
void dump_operands(ostream&out, int indent) const;
void dump_operands(ostream&out, int indent = 0) const;
private:
Expression*operand1_;
@ -111,7 +111,7 @@ class ExpArithmetic : public ExpBinary {
~ExpArithmetic();
int emit(ostream&out, Entity*ent, Architecture*arc);
void dump(ostream&out, int indent) const;
void dump(ostream&out, int indent = 0) const;
private:
fun_t fun_;
@ -126,7 +126,7 @@ class ExpInteger : public Expression {
int emit(ostream&out, Entity*ent, Architecture*arc);
bool is_primary(void) const;
bool evaluate(int64_t&val) const;
void dump(ostream&out, int indent) const;
void dump(ostream&out, int indent = 0) const;
private:
int64_t value_;
@ -142,7 +142,7 @@ class ExpLogical : public ExpBinary {
~ExpLogical();
int emit(ostream&out, Entity*ent, Architecture*arc);
void dump(ostream&out, int indent) const;
void dump(ostream&out, int indent = 0) const;
private:
fun_t fun_;
@ -162,7 +162,7 @@ class ExpName : public Expression {
public: // Base methods
int emit(ostream&out, Entity*ent, Architecture*arc);
bool is_primary(void) const;
void dump(ostream&out, int indent) const;
void dump(ostream&out, int indent = 0) const;
const char* name() const;
private:
@ -177,7 +177,7 @@ class ExpUAbs : public ExpUnary {
~ExpUAbs();
int emit(ostream&out, Entity*ent, Architecture*arc);
void dump(ostream&out, int indent) const;
void dump(ostream&out, int indent = 0) const;
};
class ExpUNot : public ExpUnary {
@ -187,7 +187,7 @@ class ExpUNot : public ExpUnary {
~ExpUNot();
int emit(ostream&out, Entity*ent, Architecture*arc);
void dump(ostream&out, int indent) const;
void dump(ostream&out, int indent = 0) const;
};
#endif

2
vhdlpp/vsignal.h
View File

@ -34,7 +34,7 @@ class Signal : public LineInfo {
int emit(ostream&out, Entity*ent, Architecture*arc);
void dump(ostream&out) const;
void dump(ostream&out, int indent = 0) const;
private:
perm_string name_;