Add regression test for implicit named port connection errors

Check that the file and line location is correct for errors
related to implicit named port connections.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/gold/br_gh939-iverilog-stderr.gold

@@ -0,0 +1,4 @@
+ivltests/br_gh939.v:10: error: Net o is not defined in this context.
+ivltests/br_gh939.v:10: error: Output port expression must support continuous assignment.
+ivltests/br_gh939.v:10:      : Port 1 (o) of M is connected to o
+2 error(s) during elaboration.

ivtest/ivltests/br_gh939.v

@@ -0,0 +1,11 @@
+// Check the line and file information for errors related to implicit named port
+// connections are correct.
+
+module M(
+  output o
+);
+endmodule
+
+module test;
+  M i_m(.o); // Error, no net named o
+endmodule

ivtest/regress-vvp.list

@@ -5,6 +5,7 @@
 array_packed_write_read		vvp_tests/array_packed_write_read.json
 br_gh13a			vvp_tests/br_gh13a.json
 br_gh13a-vlog95			vvp_tests/br_gh13a-vlog95.json
+br_gh939			vvp_tests/br_gh939.json
 case1				vvp_tests/case1.json
 case2				vvp_tests/case2.json
 case2-S				vvp_tests/case2-S.json

ivtest/vvp_tests/br_gh939.json

@@ -0,0 +1,6 @@
+{
+    "type"   : "CE",
+    "source" : "br_gh939.v",
+    "gold"   : "br_gh939",
+    "iverilog-args" : [ "-g2005-sv" ]
+}