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Add the l_impl test for the logical implication operator.

This commit is contained in:
Stephen Williams 2022-02-13 18:48:40 -08:00
parent 27d81bc610
commit 6c04749a68
2 changed files with 113 additions and 0 deletions
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112
ivtest/ivltests/l_impl.v Normal file
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@ -0,0 +1,112 @@
module top;
reg val1, val2;
reg res ;
reg pass;
initial begin
pass = 1'b1;
val1 = 1'b0;
val2 = 1'b0;
res = val1 -> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'b0 -> 1'b0 returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 -> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'b0 -> 1'b1 returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 -> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'b0 -> 1'bx returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 -> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'b0 -> 1'bz returned %b not 1'b1", res);
pass = 1'b0;
end
val1 = 1'b1;
val2 = 1'b0;
res = val1 -> val2;
if (res !== 1'b0) begin
$display("FAILED: 1'b1 -> 1'b0 returned %b not 1'b0", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 -> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'b1 -> 1'b1 returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'b1 -> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'b1 -> 1'bz returned %b not 1'bx", res);
pass = 1'b0;
end
val1 = 1'bx;
val2 = 1'b0;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bx -> 1'b0 returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 -> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'bx -> 1'b1 returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bx -> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bx -> 1'bz returned %b not 1'bx", res);
pass = 1'b0;
end
val1 = 1'bz;
val2 = 1'b0;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bz -> 1'b0 returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 -> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'bz -> 1'b1 returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bz -> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 -> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bz -> 1'bz returned %b not 1'bx", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule

1
ivtest/regress-sv.list
View File

@ -297,6 +297,7 @@ inc_dec_stmt normal,-g2009 ivltests
int_param normal,-g2009 ivltests
ishortint_test normal,-g2005-sv ivltests
iuint1 normal,-g2005-sv ivltests
l_impl normal,-g2005-sv ivltests
l_equiv normal,-g2005-sv ivltests
l_equiv_ca normal,-g2005-sv ivltests
l_equiv_const normal,-g2005-sv ivltests