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Fix calculation of verinum==verinum 

This test was way to picky about the widths of the arguments. In real
tests, the arguments may have different widths. This especially matter
when comparing unsized values.
This commit is contained in:
Stephen Williams 2008-11-27 20:14:27 -08:00
parent bd754b24f4
commit 38abe7185d
2 changed files with 24 additions and 4 deletions
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4
elab_scope.cc
View File

@ -699,6 +699,10 @@ bool PGenerate::generate_scope_case_(Design*des, NetScope*container)
NetEConst*item_value_co = dynamic_cast<NetEConst*>(item_value_ex);
assert(item_value_co);
if (debug_scopes)
cerr << get_fileline() << ": debug: Generate case "
<< "item value=" << item_value_co->value() << endl;
if (case_value_co->value() == item_value_co->value())
match_flag = true;
delete item_value_co;

24
verinum.cc
View File

@ -727,12 +727,28 @@ ostream& operator<< (ostream&o, const verinum&v)
verinum::V operator == (const verinum&left, const verinum&right)
{
if (left.len() != right.len())
return verinum::V0;
verinum::V left_pad = verinum::V0;
verinum::V right_pad = verinum::V0;
if (left.has_sign() && right.has_sign()) {
left_pad = left.get(left.len()-1);
right_pad = right.get(right.len()-1);
for (unsigned idx = 0 ; idx < left.len() ; idx += 1)
if (left[idx] != right[idx])
if (left_pad == verinum::V1 && right_pad == verinum::V0)
return verinum::V1;
if (left_pad == verinum::V0 && right_pad == verinum::V1)
return verinum::V0;
}
unsigned max_len = left.len();
if (right.len() > max_len)
max_len = right.len();
for (unsigned idx = 0 ; idx < max_len ; idx += 1) {
verinum::V left_bit = idx < left.len() ? left[idx] : left_pad;
verinum::V right_bit = idx < right.len()? right[idx] : right_pad;
if (left_bit != right_bit)
return verinum::V0;
}
return verinum::V1;
}