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Add flag to NetNet class to indicate a variable has been converted to a uwire. 

Internally we convert SystemVerilog variables that have a continuous
assignment into unresolved wires. But from a user's perspective they
are still variables, so we should refer to them as such in error
messages. This new flag lets us distinguish between such variables
and nets that were declared as uwires.
This commit is contained in:
Martin Whitaker 2024-02-02 22:00:57 +00:00
parent 5e139890b6
commit 4667927377
2 changed files with 12 additions and 3 deletions
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7
netlist.cc
View File

@ -556,7 +556,7 @@ void NetNet::calculate_slice_widths_from_packed_dims_(void)
NetNet::NetNet(NetScope*s, perm_string n, Type t,
const netranges_t&unpacked, ivl_type_t use_net_type)
: NetObj(s, n, calculate_count(unpacked)),
type_(t), port_type_(NOT_A_PORT),
type_(t), port_type_(NOT_A_PORT), coerced_to_uwire_(false),
local_flag_(false), net_type_(use_net_type),
discipline_(0), unpacked_dims_(unpacked),
eref_count_(0), lref_count_(0)
@ -579,7 +579,7 @@ NetNet::NetNet(NetScope*s, perm_string n, Type t,
NetNet::NetNet(NetScope*s, perm_string n, Type t, ivl_type_t type)
: NetObj(s, n, 1),
type_(t), port_type_(NOT_A_PORT),
type_(t), port_type_(NOT_A_PORT), coerced_to_uwire_(false),
local_flag_(false), net_type_(type),
discipline_(0),
eref_count_(0), lref_count_(0)
@ -622,6 +622,9 @@ void NetNet::type(NetNet::Type t)
if (type_ == t)
return;
if ((t == UNRESOLVED_WIRE) && ((type_ == REG) || (type_ == IMPLICIT_REG)))
coerced_to_uwire_ = true;
type_ = t;
initialize_dir_();

8
netlist.h
View File

@ -1,7 +1,7 @@
#ifndef IVL_netlist_H
#define IVL_netlist_H
/*
* Copyright (c) 1998-2023 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2024 Stephen Williams (steve@icarus.com)
* Copyright CERN 2013 / Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
@ -687,6 +687,11 @@ class NetNet : public NetObj, public PortType {
Type type() const;
void type(Type t);
// This method returns true if we have changed the net type from being
// a variable to being an unresolved wire. This happens in SystemVerilog
// when we find a continuous assignment to a variable.
bool coerced_to_uwire() { return coerced_to_uwire_; }
PortType port_type() const;
void port_type(PortType t);
@ -805,6 +810,7 @@ class NetNet : public NetObj, public PortType {
private:
Type type_ : 5;
PortType port_type_ : 3;
bool coerced_to_uwire_: 1;
bool local_flag_: 1;
ivl_type_t net_type_;
netuarray_t *array_type_ = nullptr;