Fix port signedness calculation.
This fixes the sign calculation for port padding. It also reports if the padding will be signed or not in the warning message. The inout calculation may not be correct. It requires both the signal and the port to be signed, but inout is not currently padded anyway.
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parent
b0e57a1a67
commit
c6a5a43620
32
elaborate.cc
32
elaborate.cc
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@ -1295,7 +1295,25 @@ v NOTE that this also handles the case that the
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if ((instance.count() == 1)
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&& (prts_vector_width != sig->vector_width())) {
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const char *tmp3 = rmod->ports[idx]->name.str();
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bool as_signed = false;
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if (tmp3 == 0) tmp3 = "???";
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switch (prts[0]->port_type()) {
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case NetNet::POUTPUT:
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as_signed = prts[0]->get_signed();
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break;
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case NetNet::PINPUT:
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as_signed = sig->get_signed();
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break;
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case NetNet::PINOUT:
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/* This may not be correct! */
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as_signed = prts[0]->get_signed() && sig->get_signed();
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break;
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default:
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ivl_assert(*this, 0);
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}
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cerr << get_fileline() << ": warning: Port " << (idx+1)
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<< " (" << tmp3 << ") of "
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<< type_ << " expects " << prts_vector_width <<
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@ -1316,21 +1334,21 @@ v NOTE that this also handles the case that the
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}
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// Keep the if, but delete the "} else" when fixed.
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} else if (prts_vector_width > sig->vector_width()) {
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cerr << get_fileline() << ": : Padding "
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<< (prts_vector_width-sig->vector_width())
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cerr << get_fileline() << ": : Padding ";
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if (as_signed) cerr << "(signed) ";
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cerr << (prts_vector_width-sig->vector_width())
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<< " high bits of the port."
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<< endl;
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} else {
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cerr << get_fileline() << ": : Padding "
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<< (sig->vector_width()-prts_vector_width)
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cerr << get_fileline() << ": : Padding ";
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if (as_signed) cerr << "(signed) ";
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cerr << (sig->vector_width()-prts_vector_width)
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<< " high bits of the expression."
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<< endl;
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}
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sig = resize_net_to_port_(des, scope, sig, prts_vector_width,
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prts[0]->port_type(),
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prts[0]->get_signed() &&
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sig->get_signed());
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prts[0]->port_type(), as_signed);
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}
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// Connect the sig expression that is the context of the
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