vhdlpp: Workaround to make subprograms work as if they were automatic.
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@ -32,9 +32,21 @@ int SubprogramBody::emit_package(ostream&fd) const
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for (map<perm_string,Variable*>::const_iterator cur = new_variables_.begin()
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; cur != new_variables_.end() ; ++cur) {
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// Enable reg_flag for variables
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cur->second->count_ref_sequ();
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errors += cur->second->emit(fd, NULL, NULL);
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// Enable reg_flag for variables
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cur->second->count_ref_sequ();
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errors += cur->second->emit(fd, NULL, NULL);
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}
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// Emulate automatic functions (add explicit initial value assignments)
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for (map<perm_string,Variable*>::const_iterator cur = new_variables_.begin()
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; cur != new_variables_.end() ; ++cur) {
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Variable*var = cur->second;
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if(const Expression*init = var->peek_init_expr()) {
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fd << cur->first << " = ";
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init->emit(fd, NULL, NULL);
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fd << "; -- automatic function emulation" << endl;
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}
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}
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if (statements_) {
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@ -62,7 +62,7 @@ int Signal::emit(ostream&out, Entity*ent, ScopeBase*scope)
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decl.reg_flag = true;
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errors += decl.emit(out, peek_name());
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Expression*init_expr = peek_init_expr();
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const Expression*init_expr = peek_init_expr();
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if (init_expr) {
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/* Emit initialization value for wires as a weak assignment */
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if(!decl.reg_flag && !type->type_match(&primitive_REAL))
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@ -84,7 +84,7 @@ int Variable::emit(ostream&out, Entity*ent, ScopeBase*scope)
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decl.reg_flag = true;
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errors += decl.emit(out, peek_name());
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Expression*init_expr = peek_init_expr();
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const Expression*init_expr = peek_init_expr();
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if (init_expr) {
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out << " = ";
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init_expr->emit(out, ent, scope);
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@ -46,14 +46,13 @@ class SigVarBase : public LineInfo {
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void elaborate(Entity*ent, ScopeBase*scope);
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perm_string peek_name() const { return name_; }
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const Expression* peek_init_expr() const { return init_expr_; }
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protected:
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unsigned peek_refcnt_sequ_() const { return refcnt_sequ_; }
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void type_elaborate_(VType::decl_t&decl);
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Expression* peek_init_expr() const { return init_expr_; }
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private:
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perm_string name_;
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const VType*type_;
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