luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Simplify casting code

This commit is contained in:
Nick Gasson 2008-06-23 12:21:10 +01:00
parent c9ace14c40
commit 9911939576
2 changed files with 14 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
tgt-vhdl/expr.cc
View File

@ -90,27 +90,14 @@ static vhdl_expr *translate_numeric(vhdl_expr *lhs, vhdl_expr *rhs,
{
int lwidth = lhs->get_type()->get_width();
int rwidth = rhs->get_type()->get_width();
vhdl_type ltype(VHDL_TYPE_UNSIGNED, lhs->get_type()->get_msb(),
lhs->get_type()->get_lsb());
vhdl_type rtype(VHDL_TYPE_UNSIGNED, rhs->get_type()->get_msb(),
rhs->get_type()->get_lsb());
// May need to resize the left or right hand side
if (lwidth < rwidth) {
vhdl_fcall *resize =
new vhdl_fcall("resize", vhdl_type::nsigned(rwidth));
resize->add_expr(lhs);
resize->add_expr(new vhdl_const_int(rwidth));
lhs = resize;
lhs = lhs->cast(rhs->get_type());
lwidth = rwidth;
}
else if (rwidth < lwidth) {
vhdl_fcall *resize =
new vhdl_fcall("resize", vhdl_type::nsigned(lwidth));
resize->add_expr(rhs);
resize->add_expr(new vhdl_const_int(lwidth));
rhs = resize;
rhs = rhs->cast(lhs->get_type());
rwidth = lwidth;
}

14
tgt-vhdl/vhdl_syntax.cc
View File

@ -462,8 +462,18 @@ vhdl_expr::~vhdl_expr()
*/
vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
{
if (to->get_name() == type_->get_name())
return this;
if (to->get_name() == type_->get_name()) {
if (to->get_width() == type_->get_width())
return this; // Identical
else {
vhdl_type *rtype = vhdl_type::nsigned(to->get_width());
vhdl_fcall *resize = new vhdl_fcall("Resize", rtype);
resize->add_expr(this);
resize->add_expr(new vhdl_const_int(to->get_width()));
return resize;
}
}
else if (to->get_name() == VHDL_TYPE_BOOLEAN) {
// '1' is true all else are false
vhdl_const_bit *one = new vhdl_const_bit('1');