Add `forever' statement type

tgt-vhdl/stmt.cc

@@ -559,6 +559,17 @@ int draw_while(vhdl_procedural *proc, stmt_container *container,
    return 0;
 }
 
+int draw_forever(vhdl_procedural *proc, stmt_container *container,
+                 ivl_statement_t stmt)
+{
+   vhdl_loop_stmt *loop = new vhdl_loop_stmt;
+   container->add_stmt(loop);
+
+   draw_stmt(proc, loop->get_container(), ivl_stmt_sub_stmt(stmt));
+
+   return 0;
+}
+
 /*
  * Generate VHDL statements for the given Verilog statement and
  * add them to the given VHDL process. The container is the
@@ -593,6 +604,8 @@ int draw_stmt(vhdl_procedural *proc, stmt_container *container,
       return draw_case(proc, container, stmt);
    case IVL_ST_WHILE:
       return draw_while(proc, container, stmt);
+   case IVL_ST_FOREVER:
+      return draw_forever(proc, container, stmt);
    default:
       error("No VHDL translation for statement at %s:%d (type = %d)",
             ivl_stmt_file(stmt), ivl_stmt_lineno(stmt),

tgt-vhdl/vhdl_syntax.cc

@@ -766,6 +766,13 @@ void vhdl_while_stmt::emit(std::ostream &of, int level) const
    of << "end loop;";
 }
 
+void vhdl_loop_stmt::emit(std::ostream &of, int level) const
+{
+   of << "loop";
+   stmts_.emit(of, level);
+   of << "end loop;";
+}
+
 vhdl_function::vhdl_function(const char *name, vhdl_type *ret_type)
    : vhdl_decl(name, ret_type)
 {

tgt-vhdl/vhdl_syntax.hh

@@ -408,6 +408,15 @@ private:
 };
 
 
+class vhdl_loop_stmt : public vhdl_seq_stmt {
+public:
+   stmt_container *get_container() { return &stmts_; }
+   void emit(std::ostream &of, int level) const;
+private:
+   stmt_container stmts_;
+};
+
+
 /*
  * A procedure call. Which is a statement, unlike a function
  * call which is an expression.