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luke / nextpnr
C++ 0 0
nextpnr portable FPGA place and route tool
Updated 2025-12-24 13:11:36 +01:00
luke / prjpeppercorn
Python 0 0
Project Peppercorn - GateMate FPGA Bitstream Documentation
Updated 2025-12-24 11:16:34 +01:00
luke / yosys
C++ 0 0
Yosys Open SYnthesis Suite
Updated 2025-12-24 01:26:02 +01:00
luke / verilator
SystemVerilog 0 0
Verilator open-source SystemVerilog simulator and lint system
rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog
Updated 2025-12-24 01:21:42 +01:00
luke / klayout
C++ 0 0
KLayout Main Sources
qt klayout gds2 eda
Updated 2025-12-23 18:46:08 +01:00
luke / ngspice
C 0 0
Updated 2025-12-23 11:58:13 +01:00
luke / magic
C 0 0
Magic VLSI Layout Tool
Updated 2025-12-22 15:57:56 +01:00
luke / sbt
Scala 0 0
sbt, the interactive build tool
scala zinc sbt build-tool
Updated 2025-12-20 05:46:35 +01:00
luke / xschem
C 0 0
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Updated 2025-12-19 13:06:57 +01:00
luke / openFPGALoader
C++ 0 0
Universal utility for programming FPGA
fpga xilinx bitstream trenz-gowin-littlebee arty lattice intel gowin cyclone
Updated 2025-12-17 20:07:09 +01:00
luke / iverilog
C++ 0 0
Icarus Verilog
Updated 2025-12-17 04:55:50 +01:00
luke / netgen
C 0 0
Netgen complete LVS tool for comparing SPICE or verilog netlists
Updated 2025-12-12 08:00:03 +01:00
luke / OpenSTA
C++ 0 0
OpenSTA engine
Updated 2025-12-02 17:54:43 +01:00
luke / sv2v
Haskell 0 0
SystemVerilog to Verilog conversion
verilog yosys systemverilog conversion
Updated 2025-11-24 01:25:07 +01:00
luke / IHP-AnalogAcademy
Jupyter Notebook 0 0
Updated 2025-11-18 14:17:02 +01:00
luke / OpenRAM
Python 0 0
An open-source static random access memory (SRAM) compiler.
netlists netgen magic sram gds python ngspice
Updated 2025-10-17 18:46:49 +02:00
luke / ndk-fpga
0 0
Updated 2025-06-19 20:36:45 +02:00
luke / UberDDR3
Verilog 0 0
Opensource DDR3 Controller
fpga verilog controller phy memory-controller ddr3-phy ddr3-controller ddr3
Updated 2025-06-14 05:52:13 +02:00
luke / prjxray-db
Makefile 0 0
Project X-Ray Database: XC7 Series
Updated 2025-06-05 01:06:56 +02:00
luke / prjxray
Python 0 0
Documenting the Xilinx 7-series bit-stream format.
Updated 2025-06-05 00:46:36 +02:00