Gitea: Git with a cup of tea

luke/ xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Updated 2026-09-08 19:24:19 +02:00

luke/ verilator

SystemVerilog 0 0 0

Verilator open-source SystemVerilog simulator and lint system

rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog

Updated 2026-09-08 17:08:34 +02:00

luke/ yosys

C++ 0 0 0

Yosys Open SYnthesis Suite

Updated 2026-09-08 12:31:12 +02:00

luke/ prjxray

Python 0 0 0

Documenting the Xilinx 7-series bit-stream format.

Updated 2026-09-08 10:13:39 +02:00

luke/ cxxopt

C++ 0 0 0

Lightweight C++ command line option parser

positional-arguments option-parser c-plus-plus

Updated 2026-09-08 09:57:33 +02:00

luke/ sbt

Scala 0 0 0

sbt, the interactive build tool

scala zinc sbt build-tool

Updated 2026-09-08 04:46:36 +02:00

luke/ iverilog

C++ 0 0 0

Icarus Verilog

Updated 2026-09-08 02:52:08 +02:00

luke/ prjxray-db

Shell 0 0 0

Project X-Ray Database: XC7 Series

Updated 2026-09-08 02:18:01 +02:00

luke/ ngspice

C 0 0 0

Updated 2026-09-07 22:36:36 +02:00

luke/ nextpnr

C++ 0 0 0

nextpnr portable FPGA place and route tool

Updated 2026-09-06 14:02:16 +02:00

luke/ klayout

C++ 0 0 0

KLayout Main Sources

qt klayout gds2 eda

Updated 2026-09-05 01:02:40 +02:00

luke/ OpenSTA

C++ 0 0 0

OpenSTA engine

Updated 2026-09-04 12:39:54 +02:00

luke/ openFPGALoader

C++ 0 0 0

Universal utility for programming FPGA

fpga xilinx bitstream trenz-gowin-littlebee arty lattice intel gowin cyclone

Updated 2026-09-04 12:13:36 +02:00

luke/ magic

C 0 0 0

Magic VLSI Layout Tool

Updated 2026-09-01 20:59:07 +02:00

luke/ taxi

SystemVerilog 0 0 0

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Updated 2026-08-28 22:34:16 +02:00

luke/ manta

Python 0 0 0

A configurable and approachable tool for FPGA debugging and rapid prototyping.

fpga verilog icestorm icestick debug xilinx

Updated 2026-08-26 19:08:35 +02:00

luke/ riscv-gnu-toolchain

C 0 0 0

Updated 2026-08-26 12:01:26 +02:00

luke/ IHP-AnalogAcademy

Jupyter Notebook 0 0 0

Updated 2026-08-19 12:20:48 +02:00

luke/ sv2v

Haskell 0 0 0

SystemVerilog to Verilog conversion

verilog yosys systemverilog conversion

Updated 2026-08-18 14:52:11 +02:00

luke/ abc

C 0 0 0

ABC: System for Sequential Logic Synthesis and Formal Verification

Updated 2026-08-18 12:07:47 +02:00