luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix thread modulus code to sign extend correctly. 

When the width of a long long match the vector width we do not need
to sign extend and using the << operator for this case is undefined.
This commit is contained in:
Cary R 2010-04-13 10:22:48 -07:00 committed by Stephen Williams
parent 8cbff6def0
commit 23a1ec9f53
1 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
vvp/vthread.cc
View File

@ -3439,11 +3439,13 @@ bool of_MOD_S(vthread_t thr, vvp_code_t cp)
if (rv == 0)
goto x_out;
/* Sign extend the signed operands. */
if (lv & (1LL << (cp->number-1)))
lv |= -1LL << cp->number;
if (rv & (1LL << (cp->number-1)))
rv |= -1LL << cp->number;
/* Sign extend the signed operands when needed. */
if (cp->number < 8*sizeof(long long)) {
if (lv & (1LL << (cp->number-1)))
lv |= -1LL << cp->number;
if (rv & (1LL << (cp->number-1)))
rv |= -1LL << cp->number;
}
lv %= rv;