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Handle packed structs as module outputs.

This commit is contained in:
Stephen Williams 2014-02-03 19:22:59 -08:00
parent 4f1c43b690
commit 52a9fdde8a
2 changed files with 15 additions and 5 deletions
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13
elab_lval.cc
View File

@ -789,11 +789,14 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
}
if (reg->type()==NetNet::UNRESOLVED_WIRE) {
cerr << get_fileline() << ": error: "
<< path_ << " Unable to part select unresolved wires."
<< endl;
des->errors += 1;
return false;
bool rct = reg->test_and_set_part_driver(msb, lsb);
if (rct) {
cerr << get_fileline() << ": error: "
<< path_ << "Part select is double-driving unresolved wire."
<< endl;
des->errors += 1;
return false;
}
}
const vector<netrange_t>&packed = reg->packed_dims();

7
parse.y
View File

@ -3853,8 +3853,15 @@ port_declaration
use_type = NetNet::IMPLICIT;
else
use_type = NetNet::IMPLICIT_REG;
// The SystemVerilog types that can show up as
// output ports are implicitly (on the inside)
// variables because "reg" is not valid syntax
// here.
} else if (dynamic_cast<atom2_type_t*> ($4)) {
use_type = NetNet::IMPLICIT_REG;
} else if (dynamic_cast<struct_type_t*> ($4)) {
use_type = NetNet::IMPLICIT_REG;
}
}
ptmp = pform_module_port_reference(name, @2.text, @2.first_line);