Add regression test for case muxes with array word inputs
Check that synthesized case statement muxes can use array words as inputs. This used to generate invalid VVP because .array/port statements were emitted in the middle of .functor statements. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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// Check that case statement muxes work with array word inputs.
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module test;
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reg [7:0] mem [0:3];
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reg [1:0] sel;
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reg [7:0] out;
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reg failed;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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always @* begin
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case (sel)
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2'd0: out = mem[0];
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2'd1: out = mem[1];
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2'd2: out = mem[2];
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2'd3: out = mem[3];
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endcase
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end
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(* ivl_synthesis_off *)
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initial begin
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failed = 1'b0;
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mem[0] = 8'h12;
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mem[1] = 8'h34;
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mem[2] = 8'h56;
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mem[3] = 8'h78;
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sel = 2'd0;
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#1 `check(out, 8'h12);
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sel = 2'd1;
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#1 `check(out, 8'h34);
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sel = 2'd2;
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#1 `check(out, 8'h56);
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sel = 2'd3;
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#1 `check(out, 8'h78);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -91,6 +91,7 @@ case1 vvp_tests/case1.json
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case2 vvp_tests/case2.json
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case2-S vvp_tests/case2-S.json
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case3 vvp_tests/case3.json
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case_mux_array_word vvp_tests/case_mux_array_word.json
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casex_synth vvp_tests/casex_synth.json
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cast_int_ams vvp_tests/cast_int_ams.json
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cast_real_invalid1 vvp_tests/cast_real_invalid1.json
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "case_mux_array_word.v",
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"iverilog-args" : [ "-S" ]
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}
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