Correct vector sizes for bit select

tgt-vhdl/expr.cc

@@ -157,28 +157,29 @@ static vhdl_expr *translate_binary(ivl_expr_t e)
    int lwidth = lhs->get_type()->get_width();
    int rwidth = rhs->get_type()->get_width();
 
+   std::cout << "opwidth = " << ivl_expr_width(e)
+             << " lwidth = " << lwidth
+             << " rwidth = " << rwidth << std::endl;
+   
    // May need to resize the left or right hand side
-   int opwidth;
-   if (lwidth < rwidth) {
-      rhs = rhs->cast(lhs->get_type());
-      opwidth = lwidth;
+   /*if (lwidth < rwidth) {
+      lhs = lhs->cast(rhs->get_type());
    }
    else if (rwidth < lwidth) {
-      lhs = lhs->cast(rhs->get_type());
-      opwidth = rwidth;
-   }
-   else
-      opwidth = lwidth;
+      rhs = rhs->cast(lhs->get_type());
+      }*/
 
+   int result_width = ivl_expr_width(e);
+   
    // For === and !== we need to compare std_logic_vectors
    // rather than signeds
-   vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR, opwidth-1, 0);
+   vhdl_type std_logic_vector(VHDL_TYPE_STD_LOGIC_VECTOR, result_width-1, 0);
    bool vectorop =
       (lhs->get_type()->get_name() == VHDL_TYPE_SIGNED
        || lhs->get_type()->get_name() == VHDL_TYPE_UNSIGNED) &&
       (rhs->get_type()->get_name() == VHDL_TYPE_SIGNED
        || rhs->get_type()->get_name() == VHDL_TYPE_UNSIGNED);
-      
+   
    switch (ivl_expr_opcode(e)) {
    case '+':
       return translate_numeric(lhs, rhs, VHDL_BINOP_ADD);
@@ -244,7 +245,7 @@ static vhdl_expr *translate_select(ivl_expr_t e)
    if (o2) {
       vhdl_expr *base = translate_expr(ivl_expr_oper2(e));
       if (NULL == base)
-         return NULL;   
+         return NULL;
 
       vhdl_type integer(VHDL_TYPE_INTEGER);
       from->set_slice(base->cast(&integer), ivl_expr_width(e) - 1);

tgt-vhdl/lpm.cc

@@ -90,8 +90,6 @@ static vhdl_expr *part_select_base(vhdl_scope *scope, ivl_lpm_t lpm)
 
 static vhdl_expr *draw_part_select_vp_lpm(vhdl_scope *scope, ivl_lpm_t lpm)
 {
-   std::cout << "Part select vp" << std::endl;
-   
    vhdl_var_ref *selfrom = nexus_to_var_ref(scope, ivl_lpm_data(lpm, 0));
    if (NULL == selfrom)
       return NULL;
@@ -167,8 +165,6 @@ static vhdl_expr *draw_sign_extend_lpm(vhdl_scope *scope, ivl_lpm_t lpm)
 
 vhdl_expr *lpm_to_expr(vhdl_scope *scope, ivl_lpm_t lpm)
 {
-   std::cout << "LPM type " << ivl_lpm_type(lpm) << std::endl;
-   
    switch (ivl_lpm_type(lpm)) {
    case IVL_LPM_ADD:
       return draw_binop_lpm(scope, lpm, VHDL_BINOP_ADD);

tgt-vhdl/scope.cc

@@ -63,8 +63,6 @@ static vhdl_expr *nexus_to_const(ivl_nexus_t nexus)
 static vhdl_expr *nexus_to_expr(vhdl_scope *arch_scope, ivl_nexus_t nexus,
                                 ivl_signal_t ignore = NULL)
 {
-   std::cout << "nexus_to_expr " << ivl_nexus_name(nexus) << std::endl;
-   
    int nptrs = ivl_nexus_ptrs(nexus);
    for (int i = 0; i < nptrs; i++) {
       ivl_nexus_ptr_t nexus_ptr = ivl_nexus_ptr(nexus, i);
@@ -89,7 +87,6 @@ static vhdl_expr *nexus_to_expr(vhdl_scope *arch_scope, ivl_nexus_t nexus,
          return translate_logic(arch_scope, log);
       }
       else if ((lpm = ivl_nexus_ptr_lpm(nexus_ptr))) {
-         std::cout << "LPM to expr" << std::endl;
          vhdl_expr *e = lpm_to_expr(arch_scope, lpm);
          if (e)
             return e;
@@ -254,7 +251,8 @@ static void declare_signals(vhdl_entity *ent, ivl_scope_t scope)
       ivl_signal_t sig = ivl_scope_sig(scope, i);      
       remember_signal(sig, ent->get_arch()->get_scope());
 
-      vhdl_type *sig_type = get_signal_type(sig);
+      vhdl_type *sig_type =
+         vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0);
       
       std::string name = make_safe_name(sig);
       rename_signal(sig, name);

tgt-vhdl/vhdl_syntax.cc

@@ -434,7 +434,7 @@ vhdl_expr *vhdl_expr::resize(int newwidth)
    else if (type_->get_name() == VHDL_TYPE_UNSIGNED)
       rtype = vhdl_type::nunsigned(newwidth);
    else
-      assert(false);   // Doesn't make sense to resize non-vector type
+      return this;   // Doesn't make sense to resize non-vector type
    
    vhdl_fcall *resize = new vhdl_fcall("Resize", rtype);
    resize->add_expr(this);

tgt-vhdl/vhdl_type.cc

@@ -48,14 +48,14 @@ vhdl_type *vhdl_type::integer()
    return new vhdl_type(VHDL_TYPE_INTEGER);
 }
 
-vhdl_type *vhdl_type::nunsigned(int width)
+vhdl_type *vhdl_type::nunsigned(int width, int lsb)
 {
-   return new vhdl_type(VHDL_TYPE_UNSIGNED, width-1, 0);
+   return new vhdl_type(VHDL_TYPE_UNSIGNED, width-1+lsb, lsb);
 }
 
-vhdl_type *vhdl_type::nsigned(int width)
+vhdl_type *vhdl_type::nsigned(int width, int lsb)
 {
-   return new vhdl_type(VHDL_TYPE_SIGNED, width-1, 0);
+   return new vhdl_type(VHDL_TYPE_SIGNED, width-1+lsb, lsb);
 }
 
 vhdl_type *vhdl_type::time()
@@ -122,12 +122,12 @@ vhdl_type *vhdl_type::std_logic_vector(int msb, int lsb)
    return new vhdl_type(VHDL_TYPE_STD_LOGIC_VECTOR, msb, lsb);
 }
 
-vhdl_type *vhdl_type::type_for(int width, bool issigned)
+vhdl_type *vhdl_type::type_for(int width, bool issigned, int lsb)
 {
-   if (width == 0)
+   if (width == 1)
       return vhdl_type::std_logic();
    else if (issigned)
-      return vhdl_type::nsigned(width);
+      return vhdl_type::nsigned(width, lsb);
    else
-      return vhdl_type::nunsigned(width);
+      return vhdl_type::nunsigned(width, lsb);
 }

tgt-vhdl/vhdl_type.hh

@@ -60,13 +60,13 @@ public:
    static vhdl_type *string();
    static vhdl_type *line();
    static vhdl_type *std_logic_vector(int msb, int lsb);
-   static vhdl_type *nunsigned(int width);
-   static vhdl_type *nsigned(int width);
+   static vhdl_type *nunsigned(int width, int lsb=0);
+   static vhdl_type *nsigned(int width, int lsb=0);
    static vhdl_type *integer();
    static vhdl_type *boolean();
    static vhdl_type *time();
 
-   static vhdl_type *type_for(int width, bool issigned);
+   static vhdl_type *type_for(int width, bool issigned, int lsb=0);
 protected:
    vhdl_type_name_t name_;
    int msb_, lsb_;