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Implement VHDL conf_std_logic_vector() as SystemVerilog size cast.

This commit is contained in:
Stephen Williams 2011-10-29 14:47:39 -07:00
parent 4f98a6d181
commit 37ef14b1c8
2 changed files with 17 additions and 0 deletions
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8
vhdlpp/expression_emit.cc
View File

@ -396,6 +396,14 @@ int ExpFunc::emit(ostream&out, Entity*ent, Architecture*arc)
errors += argv_[0]->emit(out, ent, arc);
out << "))";
} else if (name_ == "conv_std_logic_vector" && argv_.size() == 2) {
int64_t use_size;
bool rc = argv_[1]->evaluate(ent, arc, use_size);
ivl_assert(*this, rc);
out << use_size << "'(";
errors += argv_[0]->emit(out, ent, arc);
out << ")";
} else {
out << "\\" << name_ << " (";
for (size_t idx = 0; idx < argv_.size() ; idx += 1) {

9
vhdlpp/library.cc
View File

@ -259,6 +259,10 @@ static void import_ieee_use_std_logic_1164(ActiveScope*res, perm_string name)
}
}
static void import_ieee_use_std_logic_arith(ActiveScope*, perm_string)
{
}
static void import_ieee_use_numeric_bit(ActiveScope*res, perm_string name)
{
bool all_flag = name=="all";
@ -298,6 +302,11 @@ static void import_ieee_use(ActiveScope*res, perm_string package, perm_string na
return;
}
if (package == "std_logic_arith") {
import_ieee_use_std_logic_arith(res, name);
return;
}
if (package == "numeric_bit") {
import_ieee_use_numeric_bit(res, name);
return;