Add regression test for `output reg` syntax for UDPs

Check that it is possible to declare a registered output of a user defined
primitive using the `output reg` syntax.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-03-19 12:28:15 +01:00
parent aaffceff42
commit c5e160f1dd
2 changed files with 38 additions and 0 deletions

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@ -0,0 +1,37 @@
// Check that it is possible to have a `output reg` in a UDP defintion
module test;
reg clk = 1'b0;
reg d = 1'b0;
wire q;
dff ff(q, clk, d);
initial begin
#1
clk = 1'b1;
#1
clk = 1'b0;
d = 1'b1;
if (q === 1'b0) begin
$display("PASSED");
end else begin
$display("FAILED");
end
end
endmodule
primitive dff(q, c, d);
output reg q;
input c, d;
table
//c d : q : q+
p 0 : ? : 0 ;
p 1 : ? : 1 ;
n ? : ? : - ;
? * : ? : - ;
endtable
endprimitive

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@ -1667,6 +1667,7 @@ udp_dff normal ivltests
udp_dff_std normal ivltests
udp_eval_arg normal ivltests
udp_jkff normal ivltests
udp_output_reg normal ivltests
udp_real_delay normal ivltests
udp_sched normal ivltests
udp_x normal ivltests