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Various internal vec4 size mismatches fixed.

This commit is contained in:
Stephen Williams 2014-02-07 17:50:13 -08:00
parent c9e8392dc7
commit 554fb7ebdd
5 changed files with 15 additions and 14 deletions
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7
tgt-vvp/eval_vec4.c
View File

@ -27,7 +27,7 @@
# include <assert.h>
# include <stdbool.h>
static void resize_vec4_wid(ivl_expr_t expr, unsigned wid)
void resize_vec4_wid(ivl_expr_t expr, unsigned wid)
{
if (ivl_expr_width(expr) == wid)
return;
@ -994,11 +994,8 @@ static void draw_unary_vec4(ivl_expr_t expr, int stuff_ok_flag)
switch (ivl_expr_value(sub)) {
case IVL_VT_LOGIC:
draw_eval_vec4(sub, STUFF_OK_XZ);
if (ivl_expr_width(expr) < ivl_expr_width(sub)) {
fprintf(vvp_out, " %%pushi/vec4 0, 0, 1;\n");
fprintf(vvp_out, " %%part/u %u;\n", ivl_expr_width(expr));
}
fprintf(vvp_out, " %%cast2;\n");
resize_vec4_wid(sub, ivl_expr_width(expr));
break;
case IVL_VT_BOOL:
draw_eval_vec4(sub, 0);

10
tgt-vvp/stmt_assign.c
View File

@ -630,15 +630,7 @@ static int show_stmt_assign_vector(ivl_statement_t net)
} else {
unsigned wid = ivl_stmt_lwidth(net);
draw_eval_vec4(rval, 0);
if (ivl_expr_width(rval)==wid) {
; /* Normally, the rval expression size is correct. */
} else if (ivl_expr_signed(rval)) {
fprintf(vvp_out, " %%pad/s %u;\n", wid);
} else {
fprintf(vvp_out, " %%pad/u %u;\n", wid);
}
//res.base = 0; // XXXX This is just to suppress the clr_vector below.
//res.wid = 0;
resize_vec4_wid(rval, wid);
}
switch (ivl_stmt_opcode(net)) {

1
tgt-vvp/vvp_priv.h
View File

@ -312,6 +312,7 @@ extern uint64_t get_number_immediate64(ivl_expr_t ex);
* evaluation is the vec4 result in the top of the vec4 expression stack.
*/
extern void draw_eval_vec4(ivl_expr_t ex, int stuff_ok_flag);
extern void resize_vec4_wid(ivl_expr_t expr, unsigned wid);
/*
* draw_eval_real evaluates real value expressions. The result of the

2
tgt-vvp/vvp_process.c
View File

@ -1150,6 +1150,8 @@ static int show_stmt_cassign(ivl_statement_t net)
} else {
draw_eval_vec4(rval, STUFF_OK_47);
resize_vec4_wid(rval, ivl_stmt_lwidth(net));
/* Write out initial continuous assign instructions to assign
the expression value to the l-value. */
force_vector_to_lval(net);

9
vvp/vthread.cc
View File

@ -6002,6 +6002,10 @@ bool of_STORE_STRA(vthread_t thr, vvp_code_t cp)
/*
* %store/vec4 <var-label>, <offset>, <wid>
*
* NOTE: This instruction may loose the <wid> argument because it is
* not consistent with the %store/vec4/<etc> instructions which have
* no <wid>.
*/
bool of_STORE_VEC4(vthread_t thr, vvp_code_t cp)
{
@ -6013,6 +6017,11 @@ bool of_STORE_VEC4(vthread_t thr, vvp_code_t cp)
int off = off_index? thr->words[off_index].w_int : 0;
vvp_vector4_t val = thr->pop_vec4();
if (val.size() < wid) {
cerr << "XXXX Internal error: val.size()=" << val.size()
<< ", expecting >= " << wid << endl;
}
assert(val.size() >= wid);
if (val.size() > wid)
val.resize(wid);