Add more error checking for operators that cannot use real values.
This patch adds some checks to verify that shifts, the reduction operators and the bit wise operators are not used with real values. It also includes a few other cleanups.
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elab_net.cc
55
elab_net.cc
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@ -98,8 +98,6 @@ NetNet* PEBinary::elaborate_net(Design*des, NetScope*scope,
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case 'r': // >>
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case 'R': // >>>
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return elaborate_net_shift_(des, scope, width, rise, fall, decay);
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return 0;
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}
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/* This is an undefined operator, but we may as well check the
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@ -208,6 +206,7 @@ NetNet* PEBinary::elaborate_net_add_(Design*des, NetScope*scope,
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<< lsig->data_type() << ", right argument is "
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<< rsig->data_type() << "." << endl;
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des->errors += 1;
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return 0;
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}
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// Make the adder as wide as the widest operand
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@ -286,6 +285,24 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, NetScope*scope,
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return 0;
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}
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/* The types match here and real is not supported. */
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if (lsig->data_type() == IVL_VT_REAL) {
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char *type;
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switch (op_) {
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case '^': type = "^"; break; // XOR
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case 'X': type = "~^"; break; // XNOR
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case '&': type = "&"; break; // AND
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case 'A': type = "~&"; break; // NAND (~&)
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case '|': type = "|"; break; // Bitwise OR
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case 'O': type = "~|"; break; // Bitwise NOR
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default: assert(0);
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}
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cerr << get_fileline() << ": error: " << type
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<< " operator may not have REAL operands." << endl;
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des->errors += 1;
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return 0;
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}
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if (lsig->vector_width() != rsig->vector_width()) {
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cerr << get_fileline() << ": internal error: lsig width ("
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<< lsig->vector_width() << ") != rsig pin width ("
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@ -765,6 +782,7 @@ NetNet* PEBinary::elaborate_net_div_(Design*des, NetScope*scope,
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<< lsig->data_type() << ", right argument is "
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<< rsig->data_type() << "." << endl;
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des->errors += 1;
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return 0;
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}
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// Create a device with the calculated dimensions.
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@ -826,6 +844,7 @@ NetNet* PEBinary::elaborate_net_mod_(Design*des, NetScope*scope,
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<< lsig->data_type() << ", right argument is "
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<< rsig->data_type() << "." << endl;
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des->errors += 1;
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return 0;
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}
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/* The % operator does not support real arguments in baseline
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@ -834,6 +853,7 @@ NetNet* PEBinary::elaborate_net_mod_(Design*des, NetScope*scope,
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cerr << get_fileline() << ": error: Modulus operator may not "
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"have REAL operands." << endl;
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des->errors += 1;
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return 0;
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}
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/* rwidth is result width. */
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@ -1040,6 +1060,7 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
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<< lsig->data_type() << ", right argument is "
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<< rsig->data_type() << "." << endl;
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des->errors += 1;
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return 0;
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}
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// The mult is signed if both its operands are signed.
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@ -1105,12 +1126,14 @@ NetNet* PEBinary::elaborate_net_pow_(Design*des, NetScope*scope,
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<< lsig->data_type() << ", right argument is "
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<< rsig->data_type() << "." << endl;
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des->errors += 1;
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return 0;
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}
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/* For now we only support real values. */
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if (lsig->data_type() != IVL_VT_REAL) {
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cerr << get_fileline() << ": sorry: Bit based power (**) is "
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<< "currently unsupported in continuous assignments." << endl;
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des->errors += 1;
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return 0;
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}
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@ -1166,6 +1189,14 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
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NetNet*lsig = left_->elaborate_net(des, scope, lwidth, 0, 0, 0);
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if (lsig == 0) return 0;
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/* Cannot shift a real value. */
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if (lsig->data_type() == IVL_VT_REAL) {
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cerr << get_fileline() << ": error: shift operators "
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"cannot shift a real value." << endl;
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des->errors += 1;
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return 0;
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}
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if (lsig->vector_width() > lwidth)
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lwidth = lsig->vector_width();
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@ -1325,6 +1356,14 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
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NetNet*rsig = right_->elaborate_net(des, scope, dwid, 0, 0, 0);
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if (rsig == 0) return 0;
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/* You cannot shift a value by a real amount. */
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if (rsig->data_type() == IVL_VT_REAL) {
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cerr << get_fileline() << ": error: shift operators "
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"cannot shift by a real value." << endl;
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des->errors += 1;
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return 0;
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}
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// Make the shift device itself, and the output
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// NetNet. Connect the Result output pins to the osig signal
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NetCLShift*gate = new NetCLShift(scope, scope->local_symbol(),
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@ -3503,6 +3542,8 @@ NetNet* PEUnary::elab_net_unary_real_(Design*des, NetScope*scope,
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sig->local_flag(true);
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sig->set_line(*this);
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char *type=0;
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switch (op_) {
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default:
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@ -3510,6 +3551,16 @@ NetNet* PEUnary::elab_net_unary_real_(Design*des, NetScope*scope,
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<< op_ << " expression with real values." << endl;
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des->errors += 1;
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break;
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case '&': type = "&"; if(0){
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case 'A': type = "~&"; }if(0){
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case '|': type = "|"; }if(0){
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case 'N': type = "~|"; }if(0){
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case '^': type = "^"; }if(0){
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case 'X': type = "~^"; }
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cerr << get_fileline() << ": error: " << type
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<< " reduction operator may not have a REAL operand." << endl;
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des->errors += 1;
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break;
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case '!':
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cerr << get_fileline() << ": sorry: ! is currently unsupported"
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" for real values." << endl;
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