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Multiply nodes are always unsigned. 

It is up to the elaborator to sign-extend the inputs if the multiply
is signed in the Verilog source. The run time always processes the
multiply as unsigned.
This commit is contained in:
Stephen Williams 2008-10-11 21:08:14 -07:00
parent 995fc380e8
commit 864a86f7ee
2 changed files with 5 additions and 4 deletions
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5
ivl_target.h
View File

@ -992,8 +992,9 @@ extern unsigned ivl_lpm_lineno(ivl_lpm_t net);
* more than the width of the output, although the possibility of
* overflow exists at run time.
*
* Multiply may be signed. If so, the output should be sign extended
* to fill in its result.
* The inputs are always treated as unsigned. If the expression is
* supposed to be signed, elaboration will generate the necessary sign
* extension, so the target need not (must not) consider signedness.
*
* - Power (IVL_LPM_POW)
* The power takes two inputs and generates an output. Unlike other

4
vvp/arith.cc
View File

@ -336,13 +336,13 @@ void vvp_arith_mult::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
}
long a;
if (! vector4_to_value(op_a_, a, true, true)) {
if (! vector4_to_value(op_a_, a, false, true)) {
vvp_send_vec4(ptr.ptr()->out, x_val_);
return;
}
long b;
if (! vector4_to_value(op_b_, b, true, true)) {
if (! vector4_to_value(op_b_, b, false, true)) {
vvp_send_vec4(ptr.ptr()->out, x_val_);
return;
}