Fix blif handling of wide ligic gates.
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@ -21,26 +21,37 @@
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# include "nex_data.h"
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# include <cassert>
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static int do_print_logic_gate(FILE*fd, ivl_net_logic_t net, unsigned bit);
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int print_logic_gate(FILE*fd, ivl_net_logic_t net)
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{
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int rc = 0;
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for (unsigned idx = 0 ; idx < ivl_logic_width(net) ; idx += 1) {
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rc += do_print_logic_gate(fd, net, idx);
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if (rc != 0)
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break;
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}
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// Do not handle logic gate widths.
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assert(ivl_logic_width(net) == 1);
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return rc;
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}
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static int do_print_logic_gate(FILE*fd, ivl_net_logic_t net, unsigned bit)
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{
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int rc = 0;
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ivl_nexus_t nex_out = ivl_logic_pin(net,0);
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blif_nex_data_t*ned_out = blif_nex_data_t::get_nex_data(nex_out);
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assert(ned_out->get_width() == 1);
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assert(ned_out->get_width() > bit);
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fprintf(fd, ".names");
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for (unsigned idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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ivl_nexus_t nex = ivl_logic_pin(net,idx);
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blif_nex_data_t*ned = blif_nex_data_t::get_nex_data(nex);
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fprintf(fd, " %s", ned->get_name());
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fprintf(fd, " %s%s", ned->get_name(), ned->get_name_index(bit));
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}
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fprintf(fd, " %s", ned_out->get_name());
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fprintf(fd, " %s%s", ned_out->get_name(), ned_out->get_name_index(bit));
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fprintf(fd, "\n");
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switch (ivl_logic_type(net)) {
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