Add blif LIB_RE_* gates support.
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parent
534d44ba55
commit
999a53ab75
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@ -45,7 +45,7 @@ CXXFLAGS = @WARNING_FLAGS@ @CXXFLAGS@
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LDFLAGS = @LDFLAGS@
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O = blif.o constants.o logic_gate.o lpm.o lpm_add.o lpm_cmp_eq.o lpm_cmp_gt.o \
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lpm_part_vp.o nex_data.o
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lpm_part_vp.o lpm_re_logic.o nex_data.o
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all: dep blif.tgt
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@ -91,6 +91,14 @@ int print_lpm(FILE*fd, ivl_lpm_t net)
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case IVL_LPM_PART_VP:
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rc += print_lpm_part_vp(fd, net);
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break;
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case IVL_LPM_RE_AND:
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case IVL_LPM_RE_OR:
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case IVL_LPM_RE_XOR:
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case IVL_LPM_RE_NAND:
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case IVL_LPM_RE_NOR:
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case IVL_LPM_RE_XNOR:
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rc += print_lpm_re_logic(fd, net);
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break;
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case IVL_LPM_SUB:
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rc += print_lpm_sub(fd, net);
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break;
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@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "priv.h"
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# include "nex_data.h"
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# include <cassert>
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static bool re_xor(unsigned val)
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{
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bool flag = false;
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for (size_t idx = 0 ; idx < 8*sizeof(val) ; idx += 1) {
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if (val&1) flag ^= true;
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val >>= 1;
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}
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return flag;
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}
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int print_lpm_re_logic(FILE*fd, ivl_lpm_t net)
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{
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ivl_nexus_t nex_q = ivl_lpm_q(net);
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blif_nex_data_t*ned_q = blif_nex_data_t::get_nex_data(nex_q);
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ivl_nexus_t nex_d = ivl_lpm_data(net,0);
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blif_nex_data_t*ned_d = blif_nex_data_t::get_nex_data(nex_d);
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assert(ned_q->get_width() == 1);
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fprintf(fd, ".names");
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for (size_t idx = 0 ; idx < ned_d->get_width() ; idx += 1) {
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fprintf(fd, " %s%s", ned_d->get_name(), ned_d->get_name_index(idx));
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}
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fprintf(fd, " %s%s\n", ned_q->get_name(), ned_q->get_name_index(0));
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switch (ivl_lpm_type(net)) {
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case IVL_LPM_RE_AND:
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for (size_t idx = 0 ; idx < ned_d->get_width() ; idx += 1)
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fputc('1', fd);
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fprintf(fd, " 1\n");
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break;
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case IVL_LPM_RE_OR:
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for (size_t idx = 0 ; idx < ned_d->get_width() ; idx += 1) {
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for (size_t wid = 0 ; wid < ned_d->get_width() ; wid += 1) {
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if (wid==idx)
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fputc('1', fd);
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else
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fputc('-', fd);
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}
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fprintf(fd, " 1\n");
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}
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break;
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case IVL_LPM_RE_XOR:
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assert(ned_d->get_width() < 8*sizeof(unsigned));
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for (unsigned val = 0; val < (1U<<ned_d->get_width()); val += 1) {
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if (! re_xor(val))
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continue;
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for (size_t idx = 0 ; idx < ned_d->get_width() ; idx += 1) {
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if (val & (1<<idx))
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fputc('1', fd);
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else
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fputc('0', fd);
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}
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fprintf(fd, " 1\n");
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}
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break;
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case IVL_LPM_RE_NAND:
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for (size_t idx = 0 ; idx < ned_d->get_width() ; idx += 1) {
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for (size_t wid = 0 ; wid < ned_d->get_width() ; wid += 1) {
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if (wid==idx)
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fputc('0', fd);
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else
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fputc('-', fd);
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}
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fprintf(fd, " 1\n");
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}
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break;
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case IVL_LPM_RE_NOR:
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for (size_t idx = 0 ; idx < ned_d->get_width() ; idx += 1)
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fputc('0', fd);
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fprintf(fd, " 1\n");
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break;
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case IVL_LPM_RE_XNOR:
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assert(ned_d->get_width() < 8*sizeof(unsigned));
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for (unsigned val = 0; val < (1U<<ned_d->get_width()); val += 1) {
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if (re_xor(val))
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continue;
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for (size_t idx = 0 ; idx < ned_d->get_width() ; idx += 1) {
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if (val & (1<<idx))
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fputc('1', fd);
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else
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fputc('0', fd);
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}
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fprintf(fd, " 1\n");
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}
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break;
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default:
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assert(0);
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}
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return 0;
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}
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@ -37,6 +37,7 @@ extern int print_lpm_cmp_eq(FILE*fd, ivl_lpm_t net);
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extern int print_lpm_cmp_gt(FILE*fd, ivl_lpm_t net);
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extern int print_lpm_cmp_ne(FILE*fd, ivl_lpm_t net);
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extern int print_lpm_part_vp(FILE*fd, ivl_lpm_t net);
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extern int print_lpm_re_logic(FILE*fd, ivl_lpm_t net);
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/*
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* Emit all the constants for a model. This works by scanning the
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