Rewire VHDL addition expression parsing.
The VHDL LRM addition expression rules are ... different.
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@ -177,6 +177,8 @@ const VType*parse_type_by_name(perm_string name)
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range_t* range;
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ExpArithmetic::fun_t arithmetic_op;
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ExpAggregate::choice_t*choice;
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std::list<ExpAggregate::choice_t*>*choice_list;
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ExpAggregate::element_t*element;
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@ -225,6 +227,8 @@ const VType*parse_type_by_name(perm_string name)
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%type <flag> direction
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%type <arithmetic_op> adding_operator
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%type <interface_list> interface_element interface_list
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%type <interface_list> port_clause port_clause_opt
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%type <interface_list> generic_clause generic_clause_opt
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@ -286,6 +290,12 @@ const VType*parse_type_by_name(perm_string name)
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where I put some run-time initializations. */
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design_file : { yylloc.text = file_path; } design_units ;
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adding_operator
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: '+' { $$ = ExpArithmetic::PLUS; }
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| '-' { $$ = ExpArithmetic::MINUS; }
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| '&' { $$ = ExpArithmetic::CONCAT; }
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;
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architecture_body
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: architecture_body_start
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K_of IDENTIFIER
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@ -1705,21 +1715,21 @@ sequential_statement
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shift_expression : simple_expression { $$ = $1; } ;
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/*
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* The LRM rule for simple_expression is:
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* simple_expression ::= [sign] term { adding_operator term }
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*
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* This is functionally a list of terms, with the adding_operator used
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* as a list element separator instead of a ','. The LRM rule,
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* however, is right-recursive, which is not to nice is real LALR
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* parsers. The solution is to rewrite it as below, to make it
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* left-recursive. This is must more effecient use of the parse stack.
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*/
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simple_expression
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: term
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{ $$ = $1; }
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| term '+' term
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{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::PLUS, $1, $3);
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FILE_NAME(tmp, @2);
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$$ = tmp;
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}
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| term '-' term
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{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::MINUS, $1, $3);
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FILE_NAME(tmp, @2);
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$$ = tmp;
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}
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| term '&' term
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{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::CONCAT, $1, $3);
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| simple_expression adding_operator term
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{ ExpArithmetic*tmp = new ExpArithmetic($2, $1, $3);
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FILE_NAME(tmp, @2);
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$$ = tmp;
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}
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