Merge pull request #1199 from larsclausen/assignment-op
Add support for assignment ops on class properties and dynamic array or queue elements
This commit is contained in:
Lars-Peter Clausen
GitHub
commit
b794b9cc26
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@ -0,0 +1,58 @@
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// Check that assignment operators are supported on class properties.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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integer x;
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endclass
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integer i;
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C c;
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initial begin
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c = new;
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c.x = 1;
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c.x += 5;
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`check(c.x, 6);
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c.x -= 2;
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`check(c.x, 4);
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c.x *= 25;
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`check(c.x, 100);
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c.x /= 5;
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`check(c.x, 20);
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c.x %= 3;
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`check(c.x, 2);
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c.x = 'haa;
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c.x &= 'h33;
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`check(c.x, 'h22);
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c.x |= 'h11;
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`check(c.x, 'h33);
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c.x ^= 'h22;
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`check(c.x, 'h11);
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c.x <<= 3;
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`check(c.x, 'h88);
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c.x <<<= 1;
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`check(c.x, 'h110);
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c.x >>= 2;
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`check(c.x, 'h44);
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c.x >>>= 1;
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`check(c.x, 'h22);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,58 @@
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// Check that assignment operators are supported on static class properties.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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static integer x;
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endclass
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integer i;
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C c;
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initial begin
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c = new;
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c.x = 1;
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c.x += 5;
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`check(c.x, 6);
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c.x -= 2;
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`check(c.x, 4);
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c.x *= 25;
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`check(c.x, 100);
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c.x /= 5;
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`check(c.x, 20);
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c.x %= 3;
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`check(c.x, 2);
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c.x = 'haa;
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c.x &= 'h33;
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`check(c.x, 'h22);
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c.x |= 'h11;
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`check(c.x, 'h33);
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c.x ^= 'h22;
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`check(c.x, 'h11);
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c.x <<= 3;
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`check(c.x, 'h88);
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c.x <<<= 1;
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`check(c.x, 'h110);
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c.x >>= 2;
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`check(c.x, 'h44);
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c.x >>>= 1;
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`check(c.x, 'h22);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,86 @@
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// Check that assignment operators are supported on dynamic array elements.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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integer x[];
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integer i;
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initial begin
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x = new[2];
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// Static index
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x[1] = 1;
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x[1] += 5;
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`check(x[1], 6);
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x[1] -= 2;
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`check(x[1], 4);
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x[1] *= 25;
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`check(x[1], 100);
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x[1] /= 5;
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`check(x[1], 20);
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x[1] %= 3;
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`check(x[1], 2);
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x[1] = 'haa;
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x[1] &= 'h33;
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`check(x[1], 'h22);
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x[1] |= 'h11;
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`check(x[1], 'h33);
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x[1] ^= 'h22;
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`check(x[1], 'h11);
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x[1] <<= 3;
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`check(x[1], 'h88);
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x[1] <<<= 1;
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`check(x[1], 'h110);
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x[1] >>= 2;
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`check(x[1], 'h44);
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x[1] >>>= 1;
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`check(x[1], 'h22);
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// Dynamic index
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x[1] = 1;
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i = 1;
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x[i] += 5;
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`check(x[i], 6);
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x[i] -= 2;
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`check(x[i], 4);
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x[i] *= 25;
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`check(x[i], 100);
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x[i] /= 5;
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`check(x[i], 20);
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x[i] %= 3;
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`check(x[i], 2);
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x[i] = 'haa;
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x[i] &= 'h33;
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`check(x[i], 'h22);
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x[i] |= 'h11;
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`check(x[i], 'h33);
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x[i] ^= 'h22;
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`check(x[i], 'h11);
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x[i] <<= 3;
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`check(x[i], 'h88);
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x[i] <<<= 1;
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`check(x[i], 'h110);
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x[i] >>= 2;
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`check(x[i], 'h44);
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x[i] >>>= 1;
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`check(x[i], 'h22);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -0,0 +1,84 @@
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// Check that assignment operators are supported on queue elements.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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integer x[$];
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integer i;
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initial begin
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x = '{0, 1};
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// Static index
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x[1] += 5;
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`check(x[1], 6);
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x[1] -= 2;
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`check(x[1], 4);
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x[1] *= 25;
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`check(x[1], 100);
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x[1] /= 5;
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`check(x[1], 20);
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x[1] %= 3;
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`check(x[1], 2);
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x[1] = 'haa;
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x[1] &= 'h33;
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`check(x[1], 'h22);
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x[1] |= 'h11;
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`check(x[1], 'h33);
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x[1] ^= 'h22;
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`check(x[1], 'h11);
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x[1] <<= 3;
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`check(x[1], 'h88);
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x[1] <<<= 1;
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`check(x[1], 'h110);
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x[1] >>= 2;
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`check(x[1], 'h44);
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x[1] >>>= 1;
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`check(x[1], 'h22);
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// Dynamic index
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x[1] = 1;
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i = 1;
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x[i] += 5;
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`check(x[i], 6);
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x[i] -= 2;
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`check(x[i], 4);
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x[i] *= 25;
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`check(x[i], 100);
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x[i] /= 5;
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`check(x[i], 20);
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x[i] %= 3;
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`check(x[i], 2);
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x[i] = 'haa;
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x[i] &= 'h33;
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`check(x[i], 'h22);
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x[i] |= 'h11;
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`check(x[i], 'h33);
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x[i] ^= 'h22;
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`check(x[i], 'h11);
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x[i] <<= 3;
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`check(x[i], 'h88);
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x[i] <<<= 1;
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`check(x[i], 'h110);
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x[i] >>= 2;
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`check(x[i], 'h44);
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x[i] >>>= 1;
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`check(x[i], 'h22);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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@ -222,6 +222,8 @@ sv_chained_constructor2 vvp_tests/sv_chained_constructor2.json
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sv_chained_constructor3 vvp_tests/sv_chained_constructor3.json
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sv_chained_constructor4 vvp_tests/sv_chained_constructor4.json
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sv_chained_constructor5 vvp_tests/sv_chained_constructor5.json
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sv_class_prop_assign_op1 vvp_tests/sv_class_prop_assign_op1.json
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sv_class_prop_assign_op2 vvp_tests/sv_class_prop_assign_op2.json
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sv_class_prop_logic vvp_tests/sv_class_prop_logic.json
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sv_const1 vvp_tests/sv_const1.json
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sv_const2 vvp_tests/sv_const2.json
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@ -237,6 +239,7 @@ sv_const_fail6 vvp_tests/sv_const_fail6.json
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sv_const_fail7 vvp_tests/sv_const_fail7.json
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sv_const_fail8 vvp_tests/sv_const_fail8.json
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sv_const_fail9 vvp_tests/sv_const_fail9.json
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sv_darray_assign_op vvp_tests/sv_darray_assign_op.json
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sv_default_port_value1 vvp_tests/sv_default_port_value1.json
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sv_default_port_value2 vvp_tests/sv_default_port_value2.json
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sv_default_port_value3 vvp_tests/sv_default_port_value3.json
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@ -255,6 +258,7 @@ sv_module_port2 vvp_tests/sv_module_port2.json
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sv_module_port3 vvp_tests/sv_module_port3.json
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sv_module_port4 vvp_tests/sv_module_port4.json
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sv_parameter_type vvp_tests/sv_parameter_type.json
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sv_queue_assign_op vvp_tests/sv_queue_assign_op.json
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sv_wildcard_import8 vvp_tests/sv_wildcard_import8.json
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sdf_header vvp_tests/sdf_header.json
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task_return1 vvp_tests/task_return1.json
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_class_prop_assign_op1.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_class_prop_assign_op2.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_darray_assign_op.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -0,0 +1,5 @@
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{
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"type" : "normal",
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"source" : "sv_queue_assign_op.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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@ -541,13 +541,77 @@ static unsigned int draw_array_pattern(ivl_signal_t var, ivl_expr_t rval,
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return array_idx;
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}
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static void draw_stmt_assign_vector_opcode(unsigned char opcode, bool is_signed)
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{
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int idx_reg;
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switch (opcode) {
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case 0:
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break;
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case '+':
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fprintf(vvp_out, " %%add;\n");
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break;
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case '-':
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fprintf(vvp_out, " %%sub;\n");
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break;
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case '*':
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fprintf(vvp_out, " %%mul;\n");
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break;
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case '/':
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fprintf(vvp_out, " %%div%s;\n", is_signed ? "/s":"");
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break;
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case '%':
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fprintf(vvp_out, " %%mod%s;\n", is_signed ? "/s":"");
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break;
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case '&':
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fprintf(vvp_out, " %%and;\n");
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break;
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case '|':
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fprintf(vvp_out, " %%or;\n");
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break;
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case '^':
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fprintf(vvp_out, " %%xor;\n");
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break;
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case 'l': /* lval <<= expr */
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idx_reg = allocate_word();
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fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
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fprintf(vvp_out, " %%shiftl %d;\n", idx_reg);
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clr_word(idx_reg);
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break;
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case 'r': /* lval >>= expr */
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idx_reg = allocate_word();
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fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
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fprintf(vvp_out, " %%shiftr %d;\n", idx_reg);
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clr_word(idx_reg);
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break;
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case 'R': /* lval >>>= expr */
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idx_reg = allocate_word();
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fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
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fprintf(vvp_out, " %%shiftr/s %d;\n", idx_reg);
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clr_word(idx_reg);
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break;
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default:
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fprintf(vvp_out, "; UNSUPPORTED ASSIGNMENT OPCODE: %c\n", opcode);
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assert(0);
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break;
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}
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}
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static int show_stmt_assign_vector(ivl_statement_t net)
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{
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ivl_expr_t rval = ivl_stmt_rval(net);
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//struct vector_info res;
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//struct vector_info lres = {0, 0};
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struct vec_slice_info*slices = 0;
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int idx_reg;
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if (ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN) {
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ivl_lval_t lval = ivl_stmt_lval(net, 0);
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@ -556,96 +620,30 @@ static int show_stmt_assign_vector(ivl_statement_t net)
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return 0;
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}
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unsigned wid = ivl_stmt_lwidth(net);
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/* If this is a compressed assignment, then get the contents
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of the l-value. We need these values as part of the r-value
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calculation. */
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if (ivl_stmt_opcode(net) != 0) {
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struct vec_slice_info *slices;
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slices = calloc(ivl_stmt_lvals(net), sizeof(struct vec_slice_info));
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fprintf(vvp_out, " ; show_stmt_assign_vector: Get l-value for compressed %c= operand\n", ivl_stmt_opcode(net));
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slices = calloc(ivl_stmt_lvals(net), sizeof(struct vec_slice_info));
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get_vec_from_lval(net, slices);
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}
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unsigned wid = ivl_stmt_lwidth(net);
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draw_eval_vec4(rval);
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resize_vec4_wid(rval, wid);
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switch (ivl_stmt_opcode(net)) {
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case 0:
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draw_eval_vec4(rval);
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resize_vec4_wid(rval, wid);
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draw_stmt_assign_vector_opcode(ivl_stmt_opcode(net),
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ivl_expr_signed(rval));
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put_vec_to_lval(net, slices);
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free(slices);
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} else {
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draw_eval_vec4(rval);
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resize_vec4_wid(rval, wid);
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store_vec4_to_lval(net);
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break;
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case '+':
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fprintf(vvp_out, " %%add;\n");
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put_vec_to_lval(net, slices);
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break;
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case '-':
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fprintf(vvp_out, " %%sub;\n");
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put_vec_to_lval(net, slices);
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break;
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case '*':
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fprintf(vvp_out, " %%mul;\n");
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put_vec_to_lval(net, slices);
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break;
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case '/':
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fprintf(vvp_out, " %%div%s;\n", ivl_expr_signed(rval)? "/s":"");
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put_vec_to_lval(net, slices);
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break;
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case '%':
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||||
fprintf(vvp_out, " %%mod%s;\n", ivl_expr_signed(rval)? "/s":"");
|
||||
put_vec_to_lval(net, slices);
|
||||
break;
|
||||
|
||||
case '&':
|
||||
fprintf(vvp_out, " %%and;\n");
|
||||
put_vec_to_lval(net, slices);
|
||||
break;
|
||||
|
||||
case '|':
|
||||
fprintf(vvp_out, " %%or;\n");
|
||||
put_vec_to_lval(net, slices);
|
||||
break;
|
||||
|
||||
case '^':
|
||||
fprintf(vvp_out, " %%xor;\n");
|
||||
put_vec_to_lval(net, slices);
|
||||
break;
|
||||
|
||||
case 'l': /* lval <<= expr */
|
||||
idx_reg = allocate_word();
|
||||
fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
|
||||
fprintf(vvp_out, " %%shiftl %d;\n", idx_reg);
|
||||
clr_word(idx_reg);
|
||||
put_vec_to_lval(net, slices);
|
||||
break;
|
||||
|
||||
case 'r': /* lval >>= expr */
|
||||
idx_reg = allocate_word();
|
||||
fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
|
||||
fprintf(vvp_out, " %%shiftr %d;\n", idx_reg);
|
||||
clr_word(idx_reg);
|
||||
put_vec_to_lval(net, slices);
|
||||
break;
|
||||
|
||||
case 'R': /* lval >>>= expr */
|
||||
idx_reg = allocate_word();
|
||||
fprintf(vvp_out, " %%ix/vec4 %d;\n", idx_reg);
|
||||
fprintf(vvp_out, " %%shiftr/s %d;\n", idx_reg);
|
||||
clr_word(idx_reg);
|
||||
put_vec_to_lval(net, slices);
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(vvp_out, "; UNSUPPORTED ASSIGNMENT OPCODE: %c\n", ivl_stmt_opcode(net));
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
|
||||
if (slices) free(slices);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -817,42 +815,11 @@ static void store_real_to_lval(ivl_lval_t lval)
|
|||
clr_word(word_ix);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function assigns a value to a real variable. This is destined
|
||||
* for /dev/null when typed ivl_signal_t takes over all the real
|
||||
* variable support.
|
||||
*/
|
||||
static int show_stmt_assign_sig_real(ivl_statement_t net)
|
||||
static void draw_stmt_assign_real_opcode(unsigned char opcode)
|
||||
{
|
||||
struct real_lval_info*slice = 0;
|
||||
ivl_lval_t lval;
|
||||
|
||||
assert(ivl_stmt_lvals(net) == 1);
|
||||
lval = ivl_stmt_lval(net, 0);
|
||||
|
||||
ivl_expr_t rval = ivl_stmt_rval(net);
|
||||
if (ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN) {
|
||||
ivl_signal_t sig = ivl_lval_sig(lval);
|
||||
draw_array_pattern(sig, rval, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* If this is a compressed assignment, then get the contents
|
||||
of the l-value. We need this value as part of the r-value
|
||||
calculation. */
|
||||
if (ivl_stmt_opcode(net) != 0) {
|
||||
fprintf(vvp_out, " ; show_stmt_assign_real: Get l-value for compressed %c= operand\n", ivl_stmt_opcode(net));
|
||||
slice = calloc(1, sizeof(struct real_lval_info));
|
||||
get_real_from_lval(lval, slice);
|
||||
}
|
||||
|
||||
draw_eval_real(rval);
|
||||
|
||||
switch (ivl_stmt_opcode(net)) {
|
||||
switch (opcode) {
|
||||
case 0:
|
||||
store_real_to_lval(lval);
|
||||
if (slice) free(slice);
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case '+':
|
||||
fprintf(vvp_out, " %%add/wr;\n");
|
||||
|
|
@ -875,13 +842,47 @@ static int show_stmt_assign_sig_real(ivl_statement_t net)
|
|||
break;
|
||||
|
||||
default:
|
||||
fprintf(vvp_out, "; UNSUPPORTED ASSIGNMENT OPCODE: %c\n", ivl_stmt_opcode(net));
|
||||
fprintf(vvp_out, "; UNSUPPORTED ASSIGNMENT OPCODE: %c\n", opcode);
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This function assigns a value to a real variable. This is destined
|
||||
* for /dev/null when typed ivl_signal_t takes over all the real
|
||||
* variable support.
|
||||
*/
|
||||
static int show_stmt_assign_sig_real(ivl_statement_t net)
|
||||
{
|
||||
ivl_lval_t lval;
|
||||
|
||||
assert(ivl_stmt_lvals(net) == 1);
|
||||
lval = ivl_stmt_lval(net, 0);
|
||||
|
||||
ivl_expr_t rval = ivl_stmt_rval(net);
|
||||
if (ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN) {
|
||||
ivl_signal_t sig = ivl_lval_sig(lval);
|
||||
draw_array_pattern(sig, rval, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* If this is a compressed assignment, then get the contents
|
||||
of the l-value. We need this value as part of the r-value
|
||||
calculation. */
|
||||
if (ivl_stmt_opcode(net) != 0) {
|
||||
struct real_lval_info slice;
|
||||
|
||||
fprintf(vvp_out, " ; show_stmt_assign_real: Get l-value for compressed %c= operand\n", ivl_stmt_opcode(net));
|
||||
get_real_from_lval(lval, &slice);
|
||||
draw_eval_real(rval);
|
||||
draw_stmt_assign_real_opcode(ivl_stmt_opcode(net));
|
||||
put_real_to_lval(lval, &slice);
|
||||
} else {
|
||||
draw_eval_real(rval);
|
||||
store_real_to_lval(lval);
|
||||
}
|
||||
|
||||
put_real_to_lval(lval, slice);
|
||||
free(slice);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1019,6 +1020,84 @@ static int show_stmt_assign_darray_pattern(ivl_statement_t net)
|
|||
return errors;
|
||||
}
|
||||
|
||||
/*
|
||||
* Loading an element and updating it is identical for queues and dynamic arrays
|
||||
* and is handled here. The updated value is left on the stack and will be
|
||||
* written back using type specific functions.
|
||||
*/
|
||||
static void show_stmt_assign_sig_darray_queue_mux(ivl_statement_t net)
|
||||
{
|
||||
ivl_lval_t lval = ivl_stmt_lval(net, 0);
|
||||
ivl_signal_t var = ivl_lval_sig(lval);
|
||||
ivl_type_t var_type = ivl_signal_net_type(var);
|
||||
ivl_type_t element_type = ivl_type_element(var_type);
|
||||
ivl_expr_t mux = ivl_lval_idx(lval);
|
||||
ivl_expr_t rval = ivl_stmt_rval(net);
|
||||
|
||||
/*
|
||||
* Queue and dynamic array load and store functions expect the element
|
||||
* address in index register 3. The index expression must only be
|
||||
* evaluated once. So in case of an assignment operator it is moved to a
|
||||
* scratch register and restored to the index register once the rvalue has
|
||||
* been evaluated.
|
||||
*/
|
||||
|
||||
switch (ivl_type_base(element_type)) {
|
||||
case IVL_VT_REAL:
|
||||
if (ivl_stmt_opcode(net) != 0) {
|
||||
int mux_word = allocate_word();
|
||||
int flag = allocate_flag();
|
||||
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%ix/mov %d, 3;\n", mux_word);
|
||||
fprintf(vvp_out, " %%flag_mov %u, 4;\n", flag);
|
||||
fprintf(vvp_out, " %%load/dar/r v%p_0;\n", var);
|
||||
draw_eval_real(rval);
|
||||
draw_stmt_assign_real_opcode(ivl_stmt_opcode(net));
|
||||
fprintf(vvp_out, " %%flag_mov 4, %d;\n", flag);
|
||||
fprintf(vvp_out, " %%ix/mov 3, %d;\n", mux_word);
|
||||
clr_flag(flag);
|
||||
clr_word(mux_word);
|
||||
} else {
|
||||
draw_eval_real(rval);
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
}
|
||||
break;
|
||||
case IVL_VT_STRING:
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
draw_eval_string(rval);
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
break;
|
||||
case IVL_VT_BOOL:
|
||||
case IVL_VT_LOGIC:
|
||||
if (ivl_stmt_opcode(net) != 0) {
|
||||
int mux_word = allocate_word();
|
||||
int flag = allocate_flag();
|
||||
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%ix/mov %d, 3;\n", mux_word);
|
||||
fprintf(vvp_out, " %%flag_mov %u, 4;\n", flag);
|
||||
fprintf(vvp_out, " %%load/dar/vec4 v%p_0;\n", var);
|
||||
draw_eval_vec4(rval);
|
||||
resize_vec4_wid(rval, ivl_stmt_lwidth(net));
|
||||
draw_stmt_assign_vector_opcode(ivl_stmt_opcode(net),
|
||||
ivl_expr_signed(rval));
|
||||
fprintf(vvp_out, " %%flag_mov 4, %d;\n", flag);
|
||||
fprintf(vvp_out, " %%ix/mov 3, %d;\n", mux_word);
|
||||
clr_flag(flag);
|
||||
clr_word(mux_word);
|
||||
} else {
|
||||
draw_eval_vec4(rval);
|
||||
resize_vec4_wid(rval, ivl_stmt_lwidth(net));
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int show_stmt_assign_sig_darray(ivl_statement_t net)
|
||||
{
|
||||
int errors = 0;
|
||||
|
|
@ -1030,41 +1109,35 @@ static int show_stmt_assign_sig_darray(ivl_statement_t net)
|
|||
assert(ivl_type_base(var_type) == IVL_VT_DARRAY);
|
||||
ivl_type_t element_type = ivl_type_element(var_type);
|
||||
|
||||
ivl_expr_t mux = ivl_lval_idx(lval);
|
||||
|
||||
assert(ivl_stmt_lvals(net) == 1);
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
assert(part == 0);
|
||||
|
||||
if (mux && (ivl_type_base(element_type) == IVL_VT_REAL)) {
|
||||
draw_eval_real(rval);
|
||||
/* The %store/dar/r expects the array index to be in index
|
||||
register 3. Calculate the index in place. */
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%store/dar/r v%p_0;\n", var);
|
||||
|
||||
} else if (mux && ivl_type_base(element_type) == IVL_VT_STRING) {
|
||||
draw_eval_string(rval);
|
||||
/* The %store/dar/str expects the array index to me in index
|
||||
register 3. Calculate the index in place. */
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%store/dar/str v%p_0;\n", var);
|
||||
|
||||
} else if (mux) {
|
||||
draw_eval_vec4(rval);
|
||||
resize_vec4_wid(rval, ivl_stmt_lwidth(net));
|
||||
/* The %store/dar/vec4 expects the array index to be in index
|
||||
register 3. Calculate the index in place. */
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%store/dar/vec4 v%p_0;\n", var);
|
||||
|
||||
if (ivl_lval_idx(lval)) {
|
||||
show_stmt_assign_sig_darray_queue_mux(net);
|
||||
switch (ivl_type_base(element_type)) {
|
||||
case IVL_VT_REAL:
|
||||
fprintf(vvp_out, " %%store/dar/r v%p_0;\n", var);
|
||||
break;
|
||||
case IVL_VT_STRING:
|
||||
fprintf(vvp_out, " %%store/dar/str v%p_0;\n", var);
|
||||
break;
|
||||
case IVL_VT_BOOL:
|
||||
case IVL_VT_LOGIC:
|
||||
fprintf(vvp_out, " %%store/dar/vec4 v%p_0;\n", var);
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
} else if (ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN) {
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
/* There is no l-value mux, but the r-value is an array
|
||||
pattern. This is a special case of an assignment to
|
||||
elements of the l-value. */
|
||||
errors += show_stmt_assign_darray_pattern(net);
|
||||
|
||||
} else if (ivl_expr_type(rval) == IVL_EX_NEW) {
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
// There is no l-value mux, and the r-value expression is
|
||||
// a "new" expression. Handle this by simply storing the
|
||||
// new object to the lval.
|
||||
|
|
@ -1074,6 +1147,7 @@ static int show_stmt_assign_sig_darray(ivl_statement_t net)
|
|||
ivl_signal_basename(var));
|
||||
|
||||
} else if (ivl_expr_type(rval) == IVL_EX_SIGNAL) {
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
|
||||
// There is no l-value mux, and the r-value expression is
|
||||
// a "signal" expression. Store a duplicate into the lvalue
|
||||
|
|
@ -1087,6 +1161,7 @@ static int show_stmt_assign_sig_darray(ivl_statement_t net)
|
|||
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
|
||||
|
||||
} else {
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
// There is no l-value mux, so this must be an
|
||||
// assignment to the array as a whole. Evaluate the
|
||||
// "object", and store the evaluated result.
|
||||
|
|
@ -1177,10 +1252,7 @@ static int show_stmt_assign_sig_queue(ivl_statement_t net)
|
|||
ivl_type_t var_type= ivl_signal_net_type(var);
|
||||
ivl_type_t element_type = ivl_type_element(var_type);
|
||||
|
||||
ivl_expr_t mux = ivl_lval_idx(lval);
|
||||
|
||||
assert(ivl_stmt_lvals(net) == 1);
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
assert(part == 0);
|
||||
|
||||
assert(ivl_type_base(var_type) == IVL_VT_QUEUE);
|
||||
|
|
@ -1191,41 +1263,39 @@ static int show_stmt_assign_sig_queue(ivl_statement_t net)
|
|||
fprintf(vvp_out, " %%ix/load %d, %u, 0;\n", idx, ivl_signal_array_count(var));
|
||||
|
||||
if (ivl_expr_type(rval) == IVL_EX_NULL) {
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
errors += draw_eval_object(rval);
|
||||
fprintf(vvp_out, " %%store/obj v%p_0;\n", var);
|
||||
|
||||
} else if (mux && (ivl_type_base(element_type) == IVL_VT_REAL)) {
|
||||
draw_eval_real(rval);
|
||||
/* The %store/qdar expects the array index to be in
|
||||
index register 3. */
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%store/qdar/r v%p_0, %d;\n", var, idx);
|
||||
|
||||
} else if (mux && ivl_type_base(element_type) == IVL_VT_STRING) {
|
||||
draw_eval_string(rval);
|
||||
/* The %store/qdar expects the array index to be in
|
||||
index register 3. */
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%store/qdar/str v%p_0, %d;\n", var, idx);
|
||||
|
||||
} else if (mux) { // What is left must be some form of vector
|
||||
assert(ivl_type_base(element_type) == IVL_VT_BOOL ||
|
||||
ivl_type_base(element_type) == IVL_VT_LOGIC);
|
||||
draw_eval_vec4(rval);
|
||||
resize_vec4_wid(rval, ivl_stmt_lwidth(net));
|
||||
/* The %store/qdar expects the array index to be in
|
||||
index register 3. */
|
||||
draw_eval_expr_into_integer(mux, 3);
|
||||
fprintf(vvp_out, " %%store/qdar/v v%p_0, %d, %u;\n", var, idx,
|
||||
} else if (ivl_lval_idx(lval)) {
|
||||
show_stmt_assign_sig_darray_queue_mux(net);
|
||||
switch (ivl_type_base(element_type)) {
|
||||
case IVL_VT_REAL:
|
||||
fprintf(vvp_out, " %%store/qdar/r v%p_0, %d;\n", var, idx);
|
||||
break;
|
||||
case IVL_VT_STRING:
|
||||
fprintf(vvp_out, " %%store/qdar/str v%p_0, %d;\n", var, idx);
|
||||
break;
|
||||
case IVL_VT_BOOL:
|
||||
case IVL_VT_LOGIC:
|
||||
fprintf(vvp_out, " %%store/qdar/v v%p_0, %d, %u;\n", var, idx,
|
||||
ivl_type_packed_width(element_type));
|
||||
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
} else if (ivl_expr_type(rval) == IVL_EX_ARRAY_PATTERN) {
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
|
||||
/* There is no l-value mux, but the r-value is an array
|
||||
pattern. This is a special case of an assignment to
|
||||
the l-value. */
|
||||
errors += show_stmt_assign_queue_pattern(var, rval, element_type, idx);
|
||||
|
||||
} else {
|
||||
assert(ivl_stmt_opcode(net) == 0);
|
||||
|
||||
/* There is no l-value mux, so this must be an
|
||||
assignment to the array as a whole. Evaluate the
|
||||
"object", and store the evaluated result. */
|
||||
|
|
@ -1260,39 +1330,43 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
|
|||
ivl_type_t sig_type = ivl_signal_net_type(sig);
|
||||
ivl_type_t prop_type = ivl_type_prop_type(sig_type, prop_idx);
|
||||
|
||||
if (ivl_type_base(prop_type) == IVL_VT_BOOL) {
|
||||
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
|
||||
|
||||
if (ivl_type_base(prop_type) == IVL_VT_BOOL ||
|
||||
ivl_type_base(prop_type) == IVL_VT_LOGIC) {
|
||||
assert(ivl_type_packed_dimensions(prop_type) == 0 ||
|
||||
(ivl_type_packed_dimensions(prop_type) == 1 &&
|
||||
ivl_type_packed_msb(prop_type,0) >= ivl_type_packed_lsb(prop_type, 0)));
|
||||
|
||||
if (ivl_stmt_opcode(net) != 0) {
|
||||
fprintf(vvp_out, " %%prop/v %d;\n", prop_idx);
|
||||
}
|
||||
|
||||
draw_eval_vec4(rval);
|
||||
if (ivl_expr_value(rval)!=IVL_VT_BOOL)
|
||||
if (ivl_type_base(prop_type) == IVL_VT_BOOL &&
|
||||
ivl_expr_value(rval) != IVL_VT_BOOL)
|
||||
fprintf(vvp_out, " %%cast2;\n");
|
||||
|
||||
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
|
||||
fprintf(vvp_out, " %%store/prop/v %d, %u; Store in bool property %s\n",
|
||||
prop_idx, lwid, ivl_type_prop_name(sig_type, prop_idx));
|
||||
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
|
||||
draw_stmt_assign_vector_opcode(ivl_stmt_opcode(net),
|
||||
ivl_expr_signed(rval));
|
||||
|
||||
} else if (ivl_type_base(prop_type) == IVL_VT_LOGIC) {
|
||||
assert(ivl_type_packed_dimensions(prop_type) == 0 ||
|
||||
(ivl_type_packed_dimensions(prop_type) == 1 &&
|
||||
ivl_type_packed_msb(prop_type,0) >= ivl_type_packed_lsb(prop_type, 0)));
|
||||
|
||||
draw_eval_vec4(rval);
|
||||
|
||||
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
|
||||
fprintf(vvp_out, " %%store/prop/v %d, %u; Store in logic property %s\n",
|
||||
prop_idx, lwid, ivl_type_prop_name(sig_type, prop_idx));
|
||||
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
|
||||
|
||||
} else if (ivl_type_base(prop_type) == IVL_VT_REAL) {
|
||||
|
||||
if (ivl_stmt_opcode(net) != 0) {
|
||||
fprintf(vvp_out, " %%prop/r %d;\n", prop_idx);
|
||||
}
|
||||
|
||||
/* Calculate the real value into the real value
|
||||
stack. The %store/prop/r will pop the stack
|
||||
value. */
|
||||
draw_eval_real(rval);
|
||||
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
|
||||
|
||||
draw_stmt_assign_real_opcode(ivl_stmt_opcode(net));
|
||||
|
||||
fprintf(vvp_out, " %%store/prop/r %d;\n", prop_idx);
|
||||
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
|
||||
|
||||
|
|
@ -1302,7 +1376,6 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
|
|||
stack. The %store/prop/r will pop the stack
|
||||
value. */
|
||||
draw_eval_string(rval);
|
||||
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
|
||||
fprintf(vvp_out, " %%store/prop/str %d;\n", prop_idx);
|
||||
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
|
||||
|
||||
|
|
@ -1313,7 +1386,6 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
|
|||
/* The property is a darray, and there is no mux
|
||||
expression to the assignment is of an entire
|
||||
array object. */
|
||||
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
|
||||
errors += draw_eval_object(rval);
|
||||
fprintf(vvp_out, " %%store/prop/obj %d, %d; IVL_VT_DARRAY\n", prop_idx, idx);
|
||||
fprintf(vvp_out, " %%pop/obj 1, 0;\n");
|
||||
|
|
@ -1327,7 +1399,6 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
|
|||
}
|
||||
|
||||
/* The property is a class object. */
|
||||
fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
|
||||
errors += draw_eval_object(rval);
|
||||
if (idx_expr) draw_eval_expr_into_integer(idx_expr, idx);
|
||||
fprintf(vvp_out, " %%store/prop/obj %d, %d; IVL_VT_CLASS\n", prop_idx, idx);
|
||||
|
|
|
|||
Loading…
Reference in New Issue