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Fix for br988 - support begin/end blocks nested inside generate blocks. 

This is syntax permitted in 1364-2001 but removed in 1364-2005.

Also update the iverilog man page to document the anachronisms warning
class that warns about use of this feature when a later generation is
selected.
This commit is contained in:
Martin Whitaker 2015-08-07 22:46:09 +01:00
parent 5facf243cd
commit e98bcb61bb
2 changed files with 67 additions and 49 deletions
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11
driver/iverilog.man.in
View File

@ -1,4 +1,4 @@
.TH iverilog 1 "May 10th, 2015" "" "Version %M.%m.%n %E"
.TH iverilog 1 "Aug 7th, 2015" "" "Version %M.%m.%n %E"
.SH NAME
iverilog - Icarus Verilog compiler
@ -292,8 +292,13 @@ after a \fB\-Wall\fP argument to suppress isolated warning types.
.TP 8
.B all
This enables the implicit, portbind, select\-range, timescale, and
sensitivity\-entire\-array warning categories.
This enables the anachronisms, implicit, portbind, select\-range,
timescale, and sensitivity\-entire\-array warning categories.
.TP 8
.B anachronisms
This enables warnings for use of features that have been deprecated
or removed in the selected generation of the Verilog language.
.TP 8
.B implicit

105
parse.y
View File

@ -4782,7 +4782,7 @@ module_item
generate/endgenerate regions do not nest. Generate schemes nest,
but generate regions do not. */
| K_generate module_item_list_opt K_endgenerate
| K_generate generate_item_list_opt K_endgenerate
{ // Test for bad nesting. I understand it, but it is illegal.
if (pform_parent_generate()) {
cerr << @1 << ": error: Generate/endgenerate regions cannot nest." << endl;
@ -4819,25 +4819,6 @@ module_item
K_endcase
{ pform_endgenerate(); }
/* Handle some anachronistic syntax cases. */
| K_generate K_begin module_item_list_opt K_end K_endgenerate
{ /* Detect and warn about anachronistic begin/end use */
if (generation_flag > GN_VER2001 && warn_anachronisms) {
warn_count += 1;
cerr << @2 << ": warning: Anachronistic use of begin/end to surround generate schemes." << endl;
}
}
| K_generate K_begin ':' IDENTIFIER {
pform_start_generate_nblock(@2, $4);
} module_item_list_opt K_end K_endgenerate
{ /* Detect and warn about anachronistic named begin/end use */
if (generation_flag > GN_VER2001 && warn_anachronisms) {
warn_count += 1;
cerr << @2 << ": warning: Anachronistic use of named begin/end to surround generate schemes." << endl;
}
pform_endgenerate();
}
| modport_declaration
| package_import_declaration
@ -4922,6 +4903,16 @@ module_item
{ pform_set_timeprecision($2, true, true); }
;
module_item_list
: module_item_list module_item
| module_item
;
module_item_list_opt
: module_item_list
|
;
generate_if : K_if '(' expression ')' { pform_start_generate_if(@1, $3); } ;
generate_case_items
@ -4936,15 +4927,37 @@ generate_case_item
{ pform_endgenerate(); }
;
module_item_list
: module_item_list module_item
| module_item
;
generate_item
: module_item
/* Handle some anachronistic syntax cases. */
| K_begin generate_item_list_opt K_end
{ /* Detect and warn about anachronistic begin/end use */
if (generation_flag > GN_VER2001 && warn_anachronisms) {
warn_count += 1;
cerr << @1 << ": warning: Anachronistic use of begin/end to surround generate schemes." << endl;
}
}
| K_begin ':' IDENTIFIER {
pform_start_generate_nblock(@1, $3);
} generate_item_list_opt K_end
{ /* Detect and warn about anachronistic named begin/end use */
if (generation_flag > GN_VER2001 && warn_anachronisms) {
warn_count += 1;
cerr << @1 << ": warning: Anachronistic use of named begin/end to surround generate schemes." << endl;
}
pform_endgenerate();
}
;
module_item_list_opt
: module_item_list
|
;
generate_item_list
: generate_item_list generate_item
| generate_item
;
generate_item_list_opt
: generate_item_list
|
;
/* A generate block is the thing within a generate scheme. It may be
a single module item, an anonymous block of module items, or a
@ -4953,24 +4966,24 @@ module_item_list_opt
only need to take note here of the scope name, if any. */
generate_block
: module_item
| K_begin module_item_list_opt K_end
| K_begin ':' IDENTIFIER module_item_list_opt K_end endlabel_opt
{ pform_generate_block_name($3);
if ($6) {
if (strcmp($3,$6) != 0) {
yyerror(@6, "error: End label doesn't match "
"begin name");
}
if (! gn_system_verilog()) {
yyerror(@6, "error: Begin end labels require "
"SystemVerilog.");
}
delete[]$6;
}
delete[]$3;
}
;
: module_item
| K_begin generate_item_list_opt K_end
| K_begin ':' IDENTIFIER generate_item_list_opt K_end endlabel_opt
{ pform_generate_block_name($3);
if ($6) {
if (strcmp($3,$6) != 0) {
yyerror(@6, "error: End label doesn't match "
"begin name");
}
if (! gn_system_verilog()) {
yyerror(@6, "error: Begin end labels require "
"SystemVerilog.");
}
delete[]$6;
}
delete[]$3;
}
;
generate_block_opt : generate_block | ';' ;