Factor out common code for warning about inconsistent timescales.
Also reword the warning for SystemVerilog, where `timescale is not the only (or indeed preferred) way of specifying timescales.
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e54d19e2d2
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21
PDelays.cc
21
PDelays.cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 1999-2011 Stephen Williams (steve@icarus.com)
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* Copyright (c) 1999-2017 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -26,11 +26,6 @@
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# include "verinum.h"
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# include "netmisc.h"
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bool dly_used_no_timescale = false;
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bool dly_used_timescale = false;
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bool display_ts_dly_warning = true;
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PDelays::PDelays()
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{
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delete_flag_ = true;
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@ -80,19 +75,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, PExpr*expr)
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{
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NetExpr*dex = elab_and_eval(des, scope, expr, -1);
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/* Print a warning if we find default and `timescale based
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* delays in the design, since this is likely an error. */
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if (scope->time_from_timescale()) dly_used_timescale = true;
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else dly_used_no_timescale = true;
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if (display_ts_dly_warning &&
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dly_used_no_timescale && dly_used_timescale) {
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cerr << "warning: Found both default and "
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"`timescale based delays. Use" << endl;
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cerr << " -Wtimescale to find the "
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"module(s) with no `timescale." << endl;
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display_ts_dly_warning = false;
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}
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check_for_inconsistent_delays(scope);
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/* If the delay expression is a real constant or vector
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constant, then evaluate it, scale it to the local time
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28
elaborate.cc
28
elaborate.cc
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@ -2355,19 +2355,7 @@ static NetExpr*elaborate_delay_expr(PExpr*expr, Design*des, NetScope*scope)
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{
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NetExpr*dex = elab_and_eval(des, scope, expr, -1);
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/* Print a warning if we find default and `timescale based
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* delays in the design, since this is likely an error. */
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if (scope->time_from_timescale()) dly_used_timescale = true;
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else dly_used_no_timescale = true;
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if (display_ts_dly_warning &&
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dly_used_no_timescale && dly_used_timescale) {
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cerr << "warning: Found both default and "
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"`timescale based delays. Use" << endl;
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cerr << " -Wtimescale to find the "
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"module(s) with no `timescale." << endl;
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display_ts_dly_warning = false;
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}
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check_for_inconsistent_delays(scope);
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/* If the delay expression is a real constant or vector
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constant, then evaluate it, scale it to the local time
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@ -5415,19 +5403,7 @@ void PSpecPath::elaborate(Design*des, NetScope*scope) const
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ndelays = delays.size();
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if (ndelays > 12) ndelays = 12;
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/* Print a warning if we find default and `timescale based
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* delays in the design, since this is likely an error. */
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if (scope->time_from_timescale()) dly_used_timescale = true;
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else dly_used_no_timescale = true;
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if (display_ts_dly_warning &&
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dly_used_no_timescale && dly_used_timescale) {
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cerr << "warning: Found both default and "
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"`timescale based delays. Use" << endl;
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cerr << " -Wtimescale to find the "
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"module(s) with no `timescale." << endl;
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display_ts_dly_warning = false;
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}
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check_for_inconsistent_delays(scope);
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/* Elaborate the delay values themselves. Remember to scale
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them for the timescale/precision of the scope. */
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37
netmisc.cc
37
netmisc.cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2001-2016 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2017 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -1665,3 +1665,38 @@ NetScope* find_method_containing_scope(const LineInfo&, NetScope*scope)
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return scope;
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}
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/*
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* Print a warning if we find a mixture of default and explicit timescale
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* based delays in the design, since this is likely an error.
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*/
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void check_for_inconsistent_delays(NetScope*scope)
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{
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static bool used_implicit_timescale = false;
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static bool used_explicit_timescale = false;
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static bool display_ts_dly_warning = true;
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if (scope->time_from_timescale())
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used_explicit_timescale = true;
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else
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used_implicit_timescale = true;
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if (display_ts_dly_warning &&
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used_explicit_timescale &&
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used_implicit_timescale) {
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if (gn_system_verilog()) {
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cerr << "warning: Found both default and explicit "
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"timescale based delays. Use" << endl;
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cerr << " : -Wtimescale to find the design "
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"element(s) with no explicit" << endl;
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cerr << " : timescale." << endl;
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} else {
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cerr << "warning: Found both default and "
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"`timescale based delays. Use" << endl;
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cerr << " : -Wtimescale to find the "
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"module(s) with no `timescale." << endl;
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}
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display_ts_dly_warning = false;
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}
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}
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12
netmisc.h
12
netmisc.h
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@ -1,7 +1,7 @@
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#ifndef IVL_netmisc_H
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#define IVL_netmisc_H
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/*
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* Copyright (c) 1999-2016 Stephen Williams (steve@icarus.com)
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* Copyright (c) 1999-2017 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -378,10 +378,6 @@ const char *human_readable_op(const char op, bool unary = false);
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enum const_bool { C_NON, C_0, C_1, C_X };
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const_bool const_logical(const NetExpr*expr);
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extern bool dly_used_no_timescale;
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extern bool dly_used_timescale;
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extern bool display_ts_dly_warning;
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/*
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* When scaling a real value to a time we need to do some standard
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* processing.
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@ -409,4 +405,10 @@ extern void assign_unpacked_with_bufz(Design*des, NetScope*scope,
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extern NetPartSelect* detect_partselect_lval(Link&pin);
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/*
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* Print a warning if we find a mixture of default and explicit timescale
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* based delays in the design, since this is likely an error.
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*/
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extern void check_for_inconsistent_delays(NetScope*scope);
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#endif /* IVL_netmisc_H */
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