Fixes for wide division/modulus.
Wide division/modulus (more bits than unsigned long) gave incorrect results when both the divisor and dividend where the same. They also did not produce an error message when dividing by zero.
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Cary R
Stephen Williams
parent
d5d6aca972
commit
7e59186f1e
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@ -1081,6 +1081,11 @@ static void div_mod (vvp_vector2_t dividend, vvp_vector2_t divisor,
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quotient = vvp_vector2_t(0, dividend.size());
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if (divisor == quotient) {
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cerr << "ERROR: division by zero, exiting." << endl;
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exit(255);
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}
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if (dividend < divisor) {
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remainder = dividend;
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return;
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@ -1098,7 +1103,7 @@ static void div_mod (vvp_vector2_t dividend, vvp_vector2_t divisor,
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mask <<= 1;
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}
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while (dividend > divisor) {
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while (dividend >= divisor) {
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if (divtmp <= dividend) {
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dividend -= divtmp;
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quotient += mask;
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@ -1148,6 +1153,27 @@ bool operator > (const vvp_vector2_t&a, const vvp_vector2_t&b)
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return false;
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}
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bool operator >= (const vvp_vector2_t&a, const vvp_vector2_t&b)
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{
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const unsigned awords = (a.wid_ + vvp_vector2_t::BITS_PER_WORD-1) / vvp_vector2_t::BITS_PER_WORD;
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const unsigned bwords = (b.wid_ + vvp_vector2_t::BITS_PER_WORD-1) / vvp_vector2_t::BITS_PER_WORD;
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const unsigned words = awords > bwords? awords : bwords;
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for (unsigned idx = words ; idx > 0 ; idx -= 1) {
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unsigned long aw = (idx <= awords)? a.vec_[idx-1] : 0;
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unsigned long bw = (idx <= bwords)? b.vec_[idx-1] : 0;
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if (aw > bw)
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return true;
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if (aw < bw)
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return false;
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}
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// If the above loop finishes, then the vectors are equal.
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return true;
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}
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bool operator < (const vvp_vector2_t&a, const vvp_vector2_t&b)
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{
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const unsigned awords = (a.wid_ + vvp_vector2_t::BITS_PER_WORD-1) / vvp_vector2_t::BITS_PER_WORD;
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@ -1189,6 +1215,28 @@ bool operator <= (const vvp_vector2_t&a, const vvp_vector2_t&b)
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return true;
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}
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bool operator == (const vvp_vector2_t&a, const vvp_vector2_t&b)
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{
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const unsigned awords = (a.wid_ + vvp_vector2_t::BITS_PER_WORD-1) / vvp_vector2_t::BITS_PER_WORD;
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const unsigned bwords = (b.wid_ + vvp_vector2_t::BITS_PER_WORD-1) / vvp_vector2_t::BITS_PER_WORD;
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const unsigned words = awords > bwords? awords : bwords;
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for (unsigned idx = words ; idx > 0 ; idx -= 1) {
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unsigned long aw = (idx <= awords)? a.vec_[idx-1] : 0;
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unsigned long bw = (idx <= bwords)? b.vec_[idx-1] : 0;
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if (aw > bw)
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return false;
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if (aw < bw)
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return false;
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}
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// If the above loop finishes, then the vectors are equal.
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return true;
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}
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vvp_vector4_t vector2_to_vector4(const vvp_vector2_t&that, unsigned wid)
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{
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vvp_vector4_t res (wid);
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203
vvp/vvp_net.h
203
vvp/vvp_net.h
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@ -271,8 +271,10 @@ class vvp_vector2_t {
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friend vvp_vector2_t operator * (const vvp_vector2_t&,
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const vvp_vector2_t&);
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friend bool operator > (const vvp_vector2_t&, const vvp_vector2_t&);
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friend bool operator >= (const vvp_vector2_t&, const vvp_vector2_t&);
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friend bool operator < (const vvp_vector2_t&, const vvp_vector2_t&);
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friend bool operator <= (const vvp_vector2_t&, const vvp_vector2_t&);
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friend bool operator == (const vvp_vector2_t&, const vvp_vector2_t&);
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public:
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vvp_vector2_t();
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@ -308,9 +310,11 @@ class vvp_vector2_t {
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void copy_from_that_(const vvp_vector2_t&that);
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};
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extern bool operator < (const vvp_vector2_t&, const vvp_vector2_t&);
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extern bool operator > (const vvp_vector2_t&, const vvp_vector2_t&);
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extern bool operator >= (const vvp_vector2_t&, const vvp_vector2_t&);
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extern bool operator < (const vvp_vector2_t&, const vvp_vector2_t&);
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extern bool operator <= (const vvp_vector2_t&, const vvp_vector2_t&);
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extern bool operator == (const vvp_vector2_t&, const vvp_vector2_t&);
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extern vvp_vector2_t operator + (const vvp_vector2_t&, const vvp_vector2_t&);
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extern vvp_vector2_t operator * (const vvp_vector2_t&, const vvp_vector2_t&);
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extern vvp_vector2_t operator / (const vvp_vector2_t&, const vvp_vector2_t&);
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@ -1039,201 +1043,4 @@ inline void vvp_send_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&val,
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}
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}
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/*
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* $Log: vvp_net.h,v $
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* Revision 1.58 2007/06/12 02:36:58 steve
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* handle constant inf values.
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*
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* Revision 1.57 2007/03/22 16:08:19 steve
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* Spelling fixes from Larry
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*
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* Revision 1.56 2007/03/02 06:13:22 steve
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* Add support for edge sensitive spec paths.
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*
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* Revision 1.55 2007/02/05 01:08:10 steve
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* Handle relink of continuous assignment.
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*
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* Revision 1.54 2007/01/16 05:44:17 steve
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* Major rework of array handling. Memories are replaced with the
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* more general concept of arrays. The NetMemory and NetEMemory
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* classes are removed from the ivl core program, and the IVL_LPM_RAM
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* lpm type is removed from the ivl_target API.
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*
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* Revision 1.53 2006/12/09 19:06:53 steve
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* Handle vpiRealVal reads of signals, and real anyedge events.
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*
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* Revision 1.52 2006/08/04 04:37:37 steve
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* Support release of a for/linked reg.
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*
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* Revision 1.51 2006/06/18 04:15:50 steve
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* Add support for system functions in continuous assignments.
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*
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* Revision 1.50 2006/03/08 05:29:42 steve
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* Add support for logic parameters.
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*
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* Revision 1.49 2005/11/26 17:16:05 steve
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* Force instruction that can be indexed.
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*
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* Revision 1.48 2005/11/25 17:55:26 steve
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* Put vec8 and vec4 nets into seperate net classes.
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*
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* Revision 1.47 2005/11/10 13:27:16 steve
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* Handle very wide % and / operations using expanded vector2 support.
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*
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* Revision 1.46 2005/09/20 00:51:53 steve
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* Lazy processing of vvp_fun_part functor.
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*
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* Revision 1.45 2005/09/19 21:45:37 steve
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* Spelling patches from Larry.
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*
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* Revision 1.44 2005/08/27 02:34:43 steve
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* Bring threads into the vvp_vector4_t structure.
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*
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* Revision 1.43 2005/07/14 23:34:19 steve
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* gcc4 compile errors.
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*
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* Revision 1.42 2005/07/06 04:29:25 steve
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* Implement real valued signals and arith nodes.
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*
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* Revision 1.41 2005/06/26 01:57:22 steve
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* Make bit masks of vector4_t 64bit aware.
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*
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* Revision 1.40 2005/06/24 02:16:42 steve
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* inline the vvp_send_vec4_pv function.
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*
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* Revision 1.39 2005/06/22 18:30:12 steve
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* Inline more simple stuff, and more vector4_t by const reference for performance.
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*
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* Revision 1.38 2005/06/22 00:04:49 steve
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* Reduce vvp_vector4 copies by using const references.
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*
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* Revision 1.37 2005/06/21 22:48:23 steve
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* Optimize vvp_scalar_t handling, and fun_buf Z handling.
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*
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* Revision 1.36 2005/06/20 01:28:14 steve
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* Inline some commonly called vvp_vector4_t methods.
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*
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* Revision 1.35 2005/06/19 18:42:00 steve
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* Optimize the LOAD_VEC implementation.
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*
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* Revision 1.34 2005/06/15 00:47:15 steve
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* Resolv do not propogate inputs that do not change.
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*
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* Revision 1.33 2005/06/14 00:42:06 steve
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* Accomodate fussy compilers.
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*
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* Revision 1.32 2005/06/13 00:54:04 steve
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* More unified vec4 to hex string functions.
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*
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* Revision 1.31 2005/06/12 15:13:37 steve
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* Support resistive mos devices.
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*
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* Revision 1.30 2005/06/12 00:44:49 steve
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* Implement nmos and pmos devices.
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*
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* Revision 1.29 2005/06/02 16:02:11 steve
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* Add support for notif0/1 gates.
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* Make delay nodes support inertial delay.
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* Add the %force/link instruction.
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*
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* Revision 1.28 2005/05/24 01:43:27 steve
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* Add a sign-extension node.
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*
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* Revision 1.27 2005/05/09 00:36:58 steve
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* Force part base out of bounds if index is invalid.
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*
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* Revision 1.26 2005/05/08 23:40:14 steve
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* Add support for variable part select.
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*
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* Revision 1.25 2005/05/07 03:14:50 steve
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* ostream insert for vvp_vector4_t objects.
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*
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* Revision 1.24 2005/04/25 04:42:17 steve
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* vvp_fun_signal eliminates duplicate propagations.
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*
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* Revision 1.23 2005/04/13 06:34:20 steve
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* Add vvp driver functor for logic outputs,
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* Add ostream output operators for debugging.
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*
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* Revision 1.22 2005/04/09 05:30:38 steve
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* Default behavior for recv_vec8 methods.
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*
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* Revision 1.21 2005/04/03 05:45:51 steve
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* Rework the vvp_delay_t class.
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*
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* Revision 1.20 2005/04/01 06:02:45 steve
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* Reimplement combinational UDPs.
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*
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* Revision 1.19 2005/03/18 02:56:04 steve
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* Add support for LPM_UFUNC user defined functions.
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*
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* Revision 1.18 2005/03/12 04:27:43 steve
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* Implement VPI access to signal strengths,
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* Fix resolution of ambiguous drive pairs,
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* Fix spelling of scalar.
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*
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* Revision 1.17 2005/02/14 01:50:23 steve
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* Signals may receive part vectors from %set/x0
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* instructions. Re-implement the %set/x0 to do
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* just that. Remove the useless %set/x0/x instruction.
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*
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* Revision 1.16 2005/02/13 05:26:30 steve
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* tri0 and tri1 resolvers must replace HiZ with 0/1 after resolution.
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*
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* Revision 1.15 2005/02/12 06:13:22 steve
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* Add debug dumps for vectors, and fix vvp_scaler_t make from BIT4_X values.
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*
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* Revision 1.14 2005/02/07 22:42:42 steve
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* Add .repeat functor and BIFIF functors.
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*
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* Revision 1.13 2005/02/04 05:13:02 steve
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* Add wide .arith/mult, and vvp_vector2_t vectors.
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*
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* Revision 1.12 2005/02/03 04:55:13 steve
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* Add support for reduction logic gates.
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*
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* Revision 1.11 2005/01/30 05:06:49 steve
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* Get .arith/sub working.
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*
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* Revision 1.10 2005/01/29 17:52:06 steve
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* move AND to buitin instead of table.
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*
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* Revision 1.9 2005/01/28 05:34:25 steve
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* Add vector4 implementation of .arith/mult.
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*
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* Revision 1.8 2005/01/22 17:36:15 steve
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* .cmp/x supports signed magnitude compare.
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*
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* Revision 1.7 2005/01/16 04:19:08 steve
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* Reimplement comparators as vvp_vector4_t nodes.
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*
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* Revision 1.6 2005/01/09 20:11:16 steve
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* Add the .part/pv node and related functionality.
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*
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* Revision 1.5 2005/01/01 02:12:34 steve
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* vvp_fun_signal propagates vvp_vector8_t vectors when appropriate.
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*
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* Revision 1.4 2004/12/31 06:00:06 steve
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* Implement .resolv functors, and stub signals recv_vec8 method.
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*
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* Revision 1.3 2004/12/29 23:45:13 steve
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* Add the part concatenation node (.concat).
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*
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* Add a vvp_event_anyedge class to handle the special
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* case of .event statements of edge type. This also
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* frees the posedge/negedge types to handle all 4 inputs.
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*
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* Implement table functor recv_vec4 method to receive
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* and process vectors.
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*
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* Revision 1.2 2004/12/15 17:16:08 steve
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* Add basic force/release capabilities.
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*
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* Revision 1.1 2004/12/11 02:31:30 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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* down this path.
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*
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*/
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#endif
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