Spelling fixes.

This commit is contained in:
steve 2005-09-15 02:30:09 +00:00
parent 4dfdc147c5
commit 293976bacc
1 changed files with 2 additions and 2 deletions

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@ -70,7 +70,7 @@ Expressions in the face of real values is covered by the baseline
Verilog standard.
The bool type supports the same operators as the logic type, with the
obvious differences imposed by th limited domain.
obvious differences imposed by the limited domain.
Comparison operators (not case compare) return logic if either of
their operands is logic. If both are bool or real (including mix of
@ -81,4 +81,4 @@ Case comparison returns bool. This differs from baseline Verilog,
which strictly speaking returns a logic, but only 0 or 1 values.
All the arithmetic operators return bool if both of their operands are
bool. Otherwise, they return logic.
bool or real. Otherwise, they return logic.