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Translate logical expressions correctly. 

For logical AND/OR in VHDL both operands must be of the
same type (Boolean)
This commit is contained in:
Nick Gasson 2008-07-04 11:23:32 +01:00
parent 88816e150a
commit 96d32b29c9
1 changed files with 14 additions and 3 deletions
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17
tgt-vhdl/expr.cc
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@ -103,6 +103,17 @@ static vhdl_expr *translate_relation(vhdl_expr *lhs, vhdl_expr *rhs,
return new vhdl_binop_expr(lhs, op, r_cast, vhdl_type::boolean());
}
/*
* Like translate_relation but both operands must be Boolean.
*/
static vhdl_expr *translate_logical(vhdl_expr *lhs, vhdl_expr *rhs,
vhdl_binop_t op)
{
vhdl_type boolean(VHDL_TYPE_BOOLEAN);
return translate_relation(lhs->cast(&boolean), rhs->cast(&boolean), op);
}
static vhdl_expr *translate_shift(vhdl_expr *lhs, vhdl_expr *rhs,
vhdl_binop_t op)
{
@ -173,9 +184,9 @@ static vhdl_expr *translate_binary(ivl_expr_t e)
case '&': // Bitwise AND
return translate_numeric(lhs, rhs, VHDL_BINOP_AND);
case 'a': // Logical AND
return translate_relation(lhs, rhs, VHDL_BINOP_AND);
case 'o':
return translate_relation(lhs, rhs, VHDL_BINOP_OR);
return translate_logical(lhs, rhs, VHDL_BINOP_AND);
case 'o': // Logical OR
return translate_logical(lhs, rhs, VHDL_BINOP_OR);
case '<':
return translate_relation(lhs, rhs, VHDL_BINOP_LT);
case '>':