Fix a typo in the man page

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Konst Mayer 2019-03-13 00:14:58 +07:00
parent dc5429e5e7
commit f95ae911d0
1 changed files with 1 additions and 1 deletions

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@ -270,7 +270,7 @@ that contain Verilog source files. During elaboration, the compiler
notices the instantiation of undefined module types. If the user
specifies library search directories, the compiler will search the
directory for files with the name of the missing module type. If it
finds such a file, it loads it as a Verilog source file, they tries
finds such a file, it loads it as a Verilog source file, then tries
again to elaborate the module.
Library module files should contain only a single module, but this is