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Remove space issues
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@@ -6,7 +6,7 @@ module DFF (output reg Q, input CLK, D);
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(posedge CLK => (Q : D)) = (480, 660);
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$setup(D, posedge CLK, 576);
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endspecify
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always @(posedge CLK)
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Q <= D;
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endmodule
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