Add regression tests for checking for-loops are fully specified in SV 2009-.

This commit is contained in:
Martin Whitaker 2024-07-13 11:37:23 +01:00
parent 0695c1fe9a
commit 488fbfc412
9 changed files with 34 additions and 0 deletions

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ivltests/br_gh1143a.v:9: error: null for-loop initialization requires SystemVerilog 2012 or later.

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ivltests/br_gh1143b.v:8: error: null for-loop termination requires SystemVerilog 2012 or later.

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ivltests/br_gh1143c.v:8: error: null for-loop step requires SystemVerilog 2012 or later.

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ivltests/br_gh1143d.v:9: error: null for-loop initialization requires SystemVerilog 2012 or later.
ivltests/br_gh1143d.v:9: error: null for-loop termination requires SystemVerilog 2012 or later.
ivltests/br_gh1143d.v:9: error: null for-loop step requires SystemVerilog 2012 or later.

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@ -54,6 +54,10 @@ br_gh1143a vvp_tests/br_gh1143a.json
br_gh1143b vvp_tests/br_gh1143b.json
br_gh1143c vvp_tests/br_gh1143c.json
br_gh1143d vvp_tests/br_gh1143d.json
br_gh1143e vvp_tests/br_gh1143e.json
br_gh1143f vvp_tests/br_gh1143f.json
br_gh1143g vvp_tests/br_gh1143g.json
br_gh1143h vvp_tests/br_gh1143h.json
ca_time_real` vvp_tests/ca_time_real.json
case1 vvp_tests/case1.json
case2 vvp_tests/case2.json

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{
"type" : "CE",
"source" : "br_gh1143a.v",
"iverilog-args" : [ "-g2009" ],
"gold" : "br_gh1143e"
}

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{
"type" : "CE",
"source" : "br_gh1143b.v",
"iverilog-args" : [ "-g2009" ],
"gold" : "br_gh1143f"
}

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{
"type" : "CE",
"source" : "br_gh1143c.v",
"iverilog-args" : [ "-g2009" ],
"gold" : "br_gh1143g"
}

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{
"type" : "CE",
"source" : "br_gh1143d.v",
"iverilog-args" : [ "-g2009" ],
"gold" : "br_gh1143h"
}