Add regression tests for checking for-loops are fully specified in SV 2009-.
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ivltests/br_gh1143a.v:9: error: null for-loop initialization requires SystemVerilog 2012 or later.
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ivltests/br_gh1143b.v:8: error: null for-loop termination requires SystemVerilog 2012 or later.
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ivltests/br_gh1143c.v:8: error: null for-loop step requires SystemVerilog 2012 or later.
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ivltests/br_gh1143d.v:9: error: null for-loop initialization requires SystemVerilog 2012 or later.
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ivltests/br_gh1143d.v:9: error: null for-loop termination requires SystemVerilog 2012 or later.
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ivltests/br_gh1143d.v:9: error: null for-loop step requires SystemVerilog 2012 or later.
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@ -54,6 +54,10 @@ br_gh1143a vvp_tests/br_gh1143a.json
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br_gh1143b vvp_tests/br_gh1143b.json
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br_gh1143c vvp_tests/br_gh1143c.json
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br_gh1143d vvp_tests/br_gh1143d.json
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br_gh1143e vvp_tests/br_gh1143e.json
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br_gh1143f vvp_tests/br_gh1143f.json
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br_gh1143g vvp_tests/br_gh1143g.json
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br_gh1143h vvp_tests/br_gh1143h.json
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ca_time_real` vvp_tests/ca_time_real.json
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case1 vvp_tests/case1.json
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case2 vvp_tests/case2.json
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{
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"type" : "CE",
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"source" : "br_gh1143a.v",
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"iverilog-args" : [ "-g2009" ],
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"gold" : "br_gh1143e"
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}
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{
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"type" : "CE",
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"source" : "br_gh1143b.v",
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"iverilog-args" : [ "-g2009" ],
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"gold" : "br_gh1143f"
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}
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{
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"type" : "CE",
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"source" : "br_gh1143c.v",
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"iverilog-args" : [ "-g2009" ],
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"gold" : "br_gh1143g"
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}
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{
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"type" : "CE",
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"source" : "br_gh1143d.v",
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"iverilog-args" : [ "-g2009" ],
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"gold" : "br_gh1143h"
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}
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