Add specific BUFZ functor.
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parent
b1b93f860c
commit
8bfc75d1ee
29
vvp/logic.cc
29
vvp/logic.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: logic.cc,v 1.15 2004/12/29 23:45:13 steve Exp $"
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#ident "$Id: logic.cc,v 1.16 2004/12/31 05:56:36 steve Exp $"
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#endif
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# include "logic.h"
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@ -88,6 +88,28 @@ vvp_fun_buf::~vvp_fun_buf()
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}
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void vvp_fun_buf::recv_vec4(vvp_net_ptr_t ptr, vvp_vector4_t bit)
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{
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if (ptr.port() != 0)
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return;
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for (unsigned idx = 0 ; idx < bit.size() ; idx += 1) {
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if (bit.value(idx) == BIT4_Z)
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bit.set_bit(idx, BIT4_X);
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}
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vvp_send_vec4(ptr.ptr()->out, bit);
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}
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vvp_fun_bufz::vvp_fun_bufz()
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{
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count_functors_table += 1;
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}
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vvp_fun_bufz::~vvp_fun_bufz()
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{
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}
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void vvp_fun_bufz::recv_vec4(vvp_net_ptr_t ptr, vvp_vector4_t bit)
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{
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if (ptr.port() != 0)
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return;
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@ -123,7 +145,7 @@ void compile_functor(char*label, char*type,
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obj = new vvp_bufif_s(false,false, ostr0, ostr1);
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#endif
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} else if (strcmp(type, "BUFZ") == 0) {
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obj = new table_functor_s(ft_BUFZ);
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obj = new vvp_fun_bufz();
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#if 0
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} else if (strcmp(type, "PMOS") == 0) {
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obj = new vvp_pmos_s;
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@ -191,6 +213,9 @@ void compile_functor(char*label, char*type,
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/*
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* $Log: logic.cc,v $
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* Revision 1.16 2004/12/31 05:56:36 steve
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* Add specific BUFZ functor.
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*
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* Revision 1.15 2004/12/29 23:45:13 steve
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* Add the part concatenation node (.concat).
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*
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24
vvp/logic.h
24
vvp/logic.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: logic.h,v 1.9 2004/12/29 23:45:13 steve Exp $"
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#ident "$Id: logic.h,v 1.10 2004/12/31 05:56:36 steve Exp $"
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#endif
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# include "vvp_net.h"
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@ -48,8 +48,8 @@ class table_functor_s: public vvp_net_fun_t {
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/*
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* The buffer functor is a very primitive functor that takes the input
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* from port-0 (and only port-0) and retransmits it as a vvp_vector4_t.
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* This is intended to model the Verilog buf(Q,D) statement. This
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* device should be useful for removing strength from vectors.
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* The retransmitted vector has all Z values changed to X, just like
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* the buf(Q,D) gate in Verilog.
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*/
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class vvp_fun_buf: public vvp_net_fun_t {
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@ -62,6 +62,21 @@ class vvp_fun_buf: public vvp_net_fun_t {
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private:
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};
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/*
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* The vvp_fun_bufz is like the vvp_fun_buf, but it does not change
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* Z values to X -- it passes Z values unchanged.
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*/
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class vvp_fun_bufz: public vvp_net_fun_t {
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public:
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explicit vvp_fun_bufz();
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virtual ~vvp_fun_bufz();
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void recv_vec4(vvp_net_ptr_t p, vvp_vector4_t bit);
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private:
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};
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// table functor types
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extern const unsigned char ft_AND[];
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@ -86,6 +101,9 @@ extern const unsigned char ft_var[];
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/*
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* $Log: logic.h,v $
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* Revision 1.10 2004/12/31 05:56:36 steve
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* Add specific BUFZ functor.
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*
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* Revision 1.9 2004/12/29 23:45:13 steve
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* Add the part concatenation node (.concat).
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*
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