Add %load/avp0 opcode and fix %load/vp0.
This patch adds a new opcode %load/avp0 that is used to load a word from an array and add a value to it. %load/vp0 was changed/fixed to do the summation at the result width not the vector width. This allows small vectors to index large arrays with an offset. A few errors in the opcodes.txt file were also fixed.
This commit is contained in:
Cary R
Stephen Williams
parent
e18b64768e
commit
c899a6a52e
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@ -28,7 +28,7 @@
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static void draw_eval_expr_dest(ivl_expr_t exp, struct vector_info dest,
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int ok_flags);
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static void draw_signal_dest(ivl_expr_t exp, struct vector_info res,
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int add_index);
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int add_index, unsigned long immediate);
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int number_is_unknown(ivl_expr_t ex)
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{
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@ -1020,16 +1020,12 @@ static struct vector_info draw_load_add_immediate(ivl_expr_t le,
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unsigned long imm;
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imm = get_number_immediate(re);
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/* Load the immediate value into word register 0 */
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fprintf(vvp_out, " %%ix/load 0, %lu;\n", imm);
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lv.base = allocate_vector(wid);
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lv.wid = wid;
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/* Load the signal value with %loads that add the index
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/* Load the signal value with a %load that adds the index
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register to the value being loaded. */
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draw_signal_dest(le, lv, 0);
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draw_signal_dest(le, lv, 0, imm);
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return lv;
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}
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@ -1720,11 +1716,11 @@ void pad_expr_in_place(ivl_expr_t exp, struct vector_info res, unsigned swid)
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* offsetting the read from the lsi (least significant index) of the
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* signal.
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*
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* If the add_index is >=0, then generate a %load/vpp to add the
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* If the add_index is >=0, then generate a %load/vp0 to add the
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* word0 value to the loaded value before storing it into the destination.
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*/
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static void draw_signal_dest(ivl_expr_t exp, struct vector_info res,
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int add_index)
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int add_index, unsigned long immediate)
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{
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unsigned swid = ivl_expr_width(exp);
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ivl_signal_t sig = ivl_expr_signal(exp);
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@ -1739,16 +1735,18 @@ static void draw_signal_dest(ivl_expr_t exp, struct vector_info res,
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if (ivl_signal_array_count(sig) > 1) {
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ivl_expr_t ix = ivl_expr_oper1(exp);
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if (!number_is_immediate(ix, 8*sizeof(unsigned long))) {
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if (add_index >= 0) {
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fprintf(stderr, "%s:%u: vvp-tgt error: "
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"add_index=%d at %s:%d\n",
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ivl_expr_file(exp), ivl_expr_lineno(exp),
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add_index, __FILE__, __LINE__);
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}
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assert(add_index < 0);
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draw_eval_expr_into_integer(ix, 3);
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fprintf(vvp_out, " %%load/av %u, v%p, %u;\n",
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res.base, sig, swid);
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if (add_index < 0) {
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fprintf(vvp_out, " %%load/av %u, v%p, %u;\n",
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res.base, sig, swid);
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} else {
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assert(add_index == 0);
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/* Add an immediate value to an array value. */
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fprintf(vvp_out, " %%ix/load 0, %lu;\n", immediate);
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fprintf(vvp_out, " %%load/avp0 %u, v%p, %u;\n",
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res.base, sig, swid);
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}
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pad_expr_in_place(exp, res, swid);
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return;
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}
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@ -1772,8 +1770,11 @@ static void draw_signal_dest(ivl_expr_t exp, struct vector_info res,
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assert(add_index == 0);
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/* If this is a REG (a variable) then I can do a vector read. */
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fprintf(vvp_out, " %%ix/load 0, %lu;\n", immediate);
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fprintf(vvp_out, " %%ix/load 2, %lu;\n", res.wid);
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fprintf(vvp_out, " %%load/vp0 %u, v%p_%u, %u;\n",
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res.base, sig, word, swid);
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swid = res.wid;
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} else {
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@ -1806,7 +1807,7 @@ static struct vector_info draw_signal_expr(ivl_expr_t exp, unsigned wid,
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res.wid = wid;
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save_expression_lookaside(res.base, exp, wid);
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draw_signal_dest(exp, res, -1);
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draw_signal_dest(exp, res, -1, 0L);
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return res;
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}
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@ -2289,7 +2290,7 @@ static void draw_eval_expr_dest(ivl_expr_t exp, struct vector_info dest,
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switch (ivl_expr_type(exp)) {
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case IVL_EX_SIGNAL:
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draw_signal_dest(exp, dest, -1);
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draw_signal_dest(exp, dest, -1, 0L);
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return;
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default:
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157
vvp/codes.h
157
vvp/codes.h
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@ -1,7 +1,7 @@
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#ifndef __codes_H
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#define __codes_H
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/*
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* Copyright (c) 2001-2007 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -18,10 +18,6 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: codes.h,v 1.84 2007/06/07 03:20:15 steve Exp $"
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#endif
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# include "pointers.h"
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# include "vvp_net.h"
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@ -92,6 +88,7 @@ extern bool of_JMP0XZ(vthread_t thr, vvp_code_t code);
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extern bool of_JMP1(vthread_t thr, vvp_code_t code);
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extern bool of_JOIN(vthread_t thr, vvp_code_t code);
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extern bool of_LOAD_AV(vthread_t thr, vvp_code_t code);
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extern bool of_LOAD_AVP0(vthread_t thr, vvp_code_t code);
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extern bool of_LOAD_AVX_P(vthread_t thr, vvp_code_t code);
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extern bool of_LOAD_MV(vthread_t thr, vvp_code_t code);
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extern bool of_LOAD_NX(vthread_t thr, vvp_code_t code);
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@ -188,154 +185,4 @@ extern vvp_code_t codespace_allocate(void);
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extern vvp_code_t codespace_next(void);
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extern vvp_code_t codespace_null(void);
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/*
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* $Log: codes.h,v $
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* Revision 1.84 2007/06/07 03:20:15 steve
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* Properly handle signed conversion to real
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*
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* Revision 1.83 2007/04/14 04:43:02 steve
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* Finish up part select of array words.
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*
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* Revision 1.82 2007/02/14 05:58:14 steve
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* Add the mov/wr opcode.
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*
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* Revision 1.81 2007/01/16 05:44:16 steve
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* Major rework of array handling. Memories are replaced with the
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* more general concept of arrays. The NetMemory and NetEMemory
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* classes are removed from the ivl core program, and the IVL_LPM_RAM
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* lpm type is removed from the ivl_target API.
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*
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* Revision 1.80 2006/10/05 01:23:53 steve
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* Handle non-constant delays on indexed non-blocking assignments.
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*
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* Revision 1.79 2006/08/09 05:19:08 steve
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* Add support for real valued modulus.
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*
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* Revision 1.78 2006/02/02 02:44:00 steve
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* Allow part selects of memory words in l-values.
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*
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* Revision 1.77 2005/11/26 17:16:05 steve
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* Force instruction that can be indexed.
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*
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* Revision 1.76 2005/09/17 04:01:01 steve
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* Add the load/v.p instruction.
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*
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* Revision 1.75 2005/09/14 02:50:07 steve
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* Add word integer compares.
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*
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* Revision 1.74 2005/06/14 01:44:09 steve
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* Add the assign_v0_d instruction.
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*
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* Revision 1.73 2005/06/02 16:02:11 steve
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* Add support for notif0/1 gates.
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* Make delay nodes support inertial delay.
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* Add the %force/link instruction.
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*
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* Revision 1.72 2005/05/07 03:15:42 steve
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* Implement non-blocking part assign.
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*
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* Revision 1.71 2005/05/01 22:05:21 steve
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* Add cassign/link instruction.
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*
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* Revision 1.70 2005/03/03 04:33:10 steve
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* Rearrange how memories are supported as vvp_vector4 arrays.
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*
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* Revision 1.69 2004/12/17 04:47:47 steve
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* Replace single release with release/net and release/reg.
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*
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* Revision 1.68 2004/12/15 17:17:42 steve
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* Add the force/v instruction.
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*
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* Revision 1.67 2004/12/11 02:31:29 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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* down this path.
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*
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* Revision 1.66 2004/06/19 15:52:53 steve
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* Add signed modulus operator.
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*
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* Revision 1.65 2004/05/19 03:26:24 steve
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* Support delayed/non-blocking assignment to reals and others.
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*
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* Revision 1.64 2003/07/03 20:03:36 steve
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* Remove the vvp_cpoint_t indirect code pointer.
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*
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* Revision 1.63 2003/06/18 03:55:19 steve
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* Add arithmetic shift operators.
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*
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* Revision 1.62 2003/06/17 19:17:42 steve
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* Remove short int restrictions from vvp opcodes.
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*
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* Revision 1.61 2003/05/26 04:44:54 steve
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* Add the set/x0/x instruction.
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*
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* Revision 1.60 2003/05/07 03:39:12 steve
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* ufunc calls to functions can have scheduling complexities.
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*
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* Revision 1.59 2003/03/28 02:33:56 steve
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* Add support for division of real operands.
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*
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* Revision 1.58 2003/02/27 20:36:29 steve
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* Add the cvt/vr instruction.
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*
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* Revision 1.57 2003/02/06 17:41:47 steve
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* Add the %sub/wr instruction.
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*
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* Revision 1.56 2003/01/26 18:16:22 steve
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* Add %cvt/ir and %cvt/ri instructions, and support
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* real values passed as arguments to VPI tasks.
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*
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* Revision 1.55 2003/01/25 23:48:06 steve
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* Add thread word array, and add the instructions,
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* %add/wr, %cmp/wr, %load/wr, %mul/wr and %set/wr.
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*
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* Revision 1.54 2002/11/21 22:43:13 steve
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* %set/x0 instruction to support bounds checking.
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*
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* Revision 1.53 2002/11/08 04:59:57 steve
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* Add the %assign/v0 instruction.
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*
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* Revision 1.52 2002/11/07 02:32:39 steve
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* Add vector set and load instructions.
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*
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* Revision 1.51 2002/09/18 04:29:55 steve
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* Add support for binary NOR operator.
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*
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* Revision 1.50 2002/09/12 15:49:43 steve
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* Add support for binary nand operator.
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*
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* Revision 1.49 2002/08/28 18:38:07 steve
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* Add the %subi instruction, and use it where possible.
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*
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* Revision 1.48 2002/08/28 17:15:06 steve
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* Add the %load/nx opcode to index vpi nets.
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*
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* Revision 1.47 2002/08/22 03:38:40 steve
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* Fix behavioral eval of x?a:b expressions.
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*
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* Revision 1.46 2002/08/12 01:35:07 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.45 2002/07/05 02:50:58 steve
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* Remove the vpi object symbol table after compile.
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*
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* Revision 1.44 2002/06/02 18:55:58 steve
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* Add %cmpi/u instruction.
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*
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* Revision 1.43 2002/05/31 20:04:22 steve
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* Add the %muli instruction.
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*
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* Revision 1.42 2002/05/31 04:09:58 steve
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* Slight improvement in %mov performance.
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*
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* Revision 1.41 2002/05/29 16:29:34 steve
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* Add %addi, which is faster to simulate.
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*
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* Revision 1.40 2002/04/21 22:29:49 steve
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* Add the assign/d instruction for computed delays.
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*
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* Revision 1.39 2002/04/14 18:41:34 steve
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* Support signed integer division.
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*/
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#endif
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@ -135,6 +135,7 @@ const static struct opcode_table_s opcode_table[] = {
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{ "%jmp/1", of_JMP1, 2, {OA_CODE_PTR, OA_BIT1, OA_NONE} },
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{ "%join", of_JOIN, 0, {OA_NONE, OA_NONE, OA_NONE} },
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{ "%load/av",of_LOAD_AV,3, {OA_BIT1, OA_ARR_PTR, OA_BIT2} },
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{ "%load/avp0",of_LOAD_AVP0,3, {OA_BIT1, OA_ARR_PTR, OA_BIT2} },
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{ "%load/avx.p",of_LOAD_AVX_P,3,{OA_BIT1, OA_ARR_PTR, OA_BIT2} },
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{ "%load/mv",of_LOAD_MV,3, {OA_BIT1, OA_MEM_PTR, OA_BIT2} },
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{ "%load/nx",of_LOAD_NX,3, {OA_BIT1, OA_VPI_PTR, OA_BIT2} },
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@ -1,7 +1,6 @@
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/*
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* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
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*
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* $Id: opcodes.txt,v 1.78 2007/06/12 02:36:58 steve Exp $
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*/
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@ -315,7 +314,7 @@ bit:
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* %ix/get/s <idx>, <bit>, <wid>
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This instruction loads a thread vector starting at <bit>, size <wid>,
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into the index register <idx>. The <bit> is the lsb of the value in
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into the index register <idx>. The <bit> is the LSB of the value in
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thread bit space, and <wid> is the width of the vector.
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The function converts the 4-value bits into a binary number, without
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@ -394,9 +393,15 @@ This instruction loads a word from the specified array. The word
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address is in index register 3. The width should match the width of
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the array word.
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* %load/avp0 <bit>, <array-label>, <wid>
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This instruction is a mix of %load/av and %load/vp0. It loads an array
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value like %load/av and then adds a value from index register 0 to the
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result like %load/vp0.
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* %load/avx.p <bit>, <array-label>, <index>
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This instruction is similar ro %load/av, but it loads only a single
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This instruction is similar to %load/av, but it loads only a single
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bit, and the <index> is the selector for the bit to use. If <index> is
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out of range, then x is loaded.
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@ -426,9 +431,13 @@ functor, the the most significant bits are dropped.
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This instruction is the same as %load/v above, except that it also
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adds the integer value is index register 0 into the loaded value. The
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addition is a verilog-style add, which means that if any of the input
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addition is a Verilog-style add, which means that if any of the input
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bits are X or Z, the entire result is turned into a vector of X bits.
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Index register 2 contains the result width. The addition of the loaded
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value and the index are done at this width to avoid the problem of a
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small vector with a large immediate offset indexing an array.
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* %load/wr <bit>, <vpi-label>
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This instruction reads a real value from the vpi-like object to a word
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@ -634,7 +643,7 @@ bits are not written anywhere.
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This instruction shifts the vector left (towards more significant
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bits) by the amount in index register 0. The <bit> is the address of
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the lsb of the vector, and <wid> the width of the vector. The shift is
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the LSB of the vector, and <wid> the width of the vector. The shift is
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done in place. Zero values are shifted in.
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* %shiftr/i0 <bit>, <wid>
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@ -642,7 +651,7 @@ done in place. Zero values are shifted in.
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This instruction shifts the vector right (towards the less significant
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bits) by the amount in the index register 0. The <bit> is the address
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of the lsb of the vector, and <wid> is the width of the vector. The
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of the LSB of the vector, and <wid> is the width of the vector. The
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shift is done in place.
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%shiftr/i0 is an unsigned down shift, so zeros are shifted into the
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@ -717,15 +726,15 @@ and leaves the result in the <dst> vector. xnor is this:
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This does a bitwise exclusive or (^) of the <src> and <dst> vector,
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and leaves the result in the <dst> vector. xor is this:
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0 xnor 0 --> 0
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0 xnor 1 --> 1
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1 xnor 0 --> 1
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1 xnor 1 --> 0
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0 xor 0 --> 0
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0 xor 1 --> 1
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1 xor 0 --> 1
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1 xor 1 --> 0
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otherwise x
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/*
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* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
|
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|
|
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2001-2004 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
|
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|
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@ -16,9 +16,6 @@
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* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: vthread.cc,v 1.166 2007/06/13 01:03:57 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
# include "vthread.h"
|
||||
|
|
@ -2104,6 +2101,45 @@ bool of_LOAD_AV(vthread_t thr, vvp_code_t cp)
|
|||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* %load/avp0 <bit>, <array-label>, <wid> ;
|
||||
*
|
||||
* <bit> is the thread bit address for the result
|
||||
* <array-label> is the array to access, and
|
||||
* <wid> is the width of the word to read.
|
||||
*
|
||||
* The address of the word in the array is in index register 3.
|
||||
* An integer value from index register 0 is added to the value.
|
||||
*/
|
||||
bool of_LOAD_AVP0(vthread_t thr, vvp_code_t cp)
|
||||
{
|
||||
unsigned bit = cp->bit_idx[0];
|
||||
unsigned wid = cp->bit_idx[1];
|
||||
int64_t addend = thr->words[0].w_int;
|
||||
unsigned adr = thr->words[3].w_int;
|
||||
|
||||
vvp_vector4_t word = array_get_word(cp->array, adr);
|
||||
|
||||
if (word.size() != wid) {
|
||||
fprintf(stderr, "internal error: array width=%u, word.size()=%u, wid=%u\n",
|
||||
0, word.size(), wid);
|
||||
}
|
||||
assert(word.size() == wid);
|
||||
|
||||
/* Add the addend value */
|
||||
word += addend;
|
||||
|
||||
/* Check the address once, before we scan the vector. */
|
||||
thr_check_addr(thr, bit+wid-1);
|
||||
|
||||
/* Copy the vector bits into the bits4 vector. Do the copy
|
||||
directly to skip the excess calls to thr_check_addr. */
|
||||
thr->bits4.set_vec(bit, word);
|
||||
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* %load/avx.p <bit>, <array-label>, <idx> ;
|
||||
*
|
||||
|
|
@ -2229,6 +2265,7 @@ vvp_vector4_t load_base(vthread_t thr, vvp_code_t cp)
|
|||
}
|
||||
assert(sig);
|
||||
|
||||
|
||||
vvp_vector4_t sig_value = sig->vec4_value();
|
||||
sig_value.resize(wid);
|
||||
|
||||
|
|
@ -2253,15 +2290,19 @@ bool of_LOAD_VEC(vthread_t thr, vvp_code_t cp)
|
|||
}
|
||||
|
||||
/*
|
||||
* This is like of_LOAD_VEC, but includes an add of an integer value.
|
||||
*/
|
||||
* This is like of_LOAD_VEC, but includes an add of an integer value from
|
||||
* index 0. The <wid> is the expected result width not the vector width.
|
||||
*/
|
||||
bool of_LOAD_VP0(vthread_t thr, vvp_code_t cp)
|
||||
{
|
||||
unsigned bit = cp->bit_idx[0];
|
||||
unsigned wid = cp->bit_idx[1];
|
||||
int64_t addend = thr->words[0].w_int;
|
||||
unsigned wid = thr->words[2].w_int;
|
||||
|
||||
vvp_vector4_t sig_value = load_base(thr, cp);
|
||||
/* We need a vector this wide to make the math work correctly.
|
||||
* Copy the base bits into the vector, but keep the width. */
|
||||
vvp_vector4_t sig_value(wid, BIT4_0);
|
||||
sig_value.copy_bits(load_base(thr, cp));
|
||||
|
||||
/* Add the addend value */
|
||||
sig_value += addend;
|
||||
|
|
@ -3646,7 +3687,3 @@ bool of_JOIN_UFUNC(vthread_t thr, vvp_code_t cp)
|
|||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* $Log: vthread.cc,v $
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2007 Stephen Williams (steve@icarus.com)
|
||||
* Copyright (c) 2004-2008 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
|
|
@ -202,6 +202,14 @@ void vvp_send_long(vvp_net_ptr_t ptr, long val)
|
|||
}
|
||||
}
|
||||
|
||||
void vvp_vector4_t::copy_bits(const vvp_vector4_t&that)
|
||||
{
|
||||
unsigned bits_to_copy = (that.size_ < size_) ? that.size_ : size_;
|
||||
|
||||
for (unsigned idx = 0; idx < bits_to_copy; idx += 1)
|
||||
set_bit(idx, that.value(idx));
|
||||
}
|
||||
|
||||
void vvp_vector4_t::copy_from_(const vvp_vector4_t&that)
|
||||
{
|
||||
size_ = that.size_;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef __vvp_net_H
|
||||
#define __vvp_net_H
|
||||
/*
|
||||
* Copyright (c) 2004-2005 Stephen Williams (steve@icarus.com)
|
||||
* Copyright (c) 2004-2008 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
|
|
@ -18,7 +18,6 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ident "$Id: vvp_net.h,v 1.58 2007/06/12 02:36:58 steve Exp $"
|
||||
|
||||
# include "config.h"
|
||||
# include <stddef.h>
|
||||
|
|
@ -118,6 +117,9 @@ class vvp_vector4_t {
|
|||
void set_bit(unsigned idx, vvp_bit4_t val);
|
||||
void set_vec(unsigned idx, const vvp_vector4_t&that);
|
||||
|
||||
// Get the bits from another vector, but keep my size.
|
||||
void copy_bits(const vvp_vector4_t&that);
|
||||
|
||||
// Test that the vectors are exactly equal
|
||||
bool eeq(const vvp_vector4_t&that) const;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue