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Allow `shortreal` module ports 

Currently there is a restriction in the parser that rejects `shortreal`
typed module ports. And while at the moment `shortreal` signals are
implemented as `real` typed signals, which is not standard compliant, there
is nothing special about module ports in this regard.

Note that support for `shortreal` (and `real`) nets is an Icarus extension,
but ports can also be variables, in which case a shortreal port is allowed
by the LRM.

`shortreal` variables and nets are allowed everywhere else. There is no
good reason to not allow them for module ports, so remove the restriction.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2022-04-19 11:45:54 +02:00
parent 5da2951c12
commit 854422a3eb
1 changed files with 1 additions and 7 deletions
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8
pform.cc
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@ -2574,16 +2574,10 @@ void pform_module_define_port(const struct vlltype&li,
signed_flag = vec_type->signed_flag;
prange = vec_type->pdims.get();
vtype = 0;
} else if (real_type_t*rtype = dynamic_cast<real_type_t*>(vtype)) {
} else if (dynamic_cast<real_type_t*>(vtype)) {
data_type = IVL_VT_REAL;
signed_flag = true;
prange = 0;
if (rtype->type_code() != real_type_t::REAL) {
VLerror(li, "sorry: Only real (not shortreal) supported here (%s:%d).",
__FILE__, __LINE__);
}
} else if (vtype) {
if (vtype->figure_packed_base_type() != IVL_VT_NO_TYPE) {
data_type = vtype->figure_packed_base_type();