tgt-vhdl: Fix shift2 test regression
Caused by translate_select emitting a logical instead of arithmetic shift for signed arguments.
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@ -473,8 +473,18 @@ static vhdl_expr *translate_select(ivl_expr_t e)
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// We can't directly select bits from something that's not
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// a variable reference in VHDL, but we can emulate the
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// effect with a shift and a resize
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return new vhdl_binop_expr(from, VHDL_BINOP_SR, base->to_integer(),
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new vhdl_type(*from->get_type()));
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if (ivl_expr_signed(ivl_expr_oper1(e))) {
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vhdl_fcall *sra = new vhdl_fcall("shift_right", from->get_type());
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sra->add_expr(from);
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sra->add_expr(base->to_integer());
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return sra;
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}
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else
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return new vhdl_binop_expr(from, VHDL_BINOP_SR, base->to_integer(),
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from->get_type());
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}
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else if (from_var_ref->get_type()->get_name() != VHDL_TYPE_STD_LOGIC) {
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// We can use the more idiomatic VHDL slice notation on a
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@ -923,7 +923,7 @@ void vhdl_unaryop_expr::emit(std::ostream &of, int level) const
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}
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vhdl_binop_expr::vhdl_binop_expr(vhdl_expr *left, vhdl_binop_t op,
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vhdl_expr *right, vhdl_type *type)
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vhdl_expr *right, const vhdl_type *type)
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: vhdl_expr(type), op_(op)
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{
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add_expr(left);
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@ -119,10 +119,10 @@ enum vhdl_binop_t {
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*/
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class vhdl_binop_expr : public vhdl_expr {
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public:
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vhdl_binop_expr(vhdl_binop_t op, vhdl_type *type)
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vhdl_binop_expr(vhdl_binop_t op, const vhdl_type *type)
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: vhdl_expr(type), op_(op) {}
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vhdl_binop_expr(vhdl_expr *left, vhdl_binop_t op,
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vhdl_expr *right, vhdl_type *type);
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vhdl_expr *right, const vhdl_type *type);
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~vhdl_binop_expr();
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void add_expr(vhdl_expr *e);
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@ -271,7 +271,7 @@ private:
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*/
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class vhdl_fcall : public vhdl_expr {
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public:
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vhdl_fcall(const string& name, vhdl_type *rtype)
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vhdl_fcall(const string& name, const vhdl_type *rtype)
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: vhdl_expr(rtype), name_(name) {};
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~vhdl_fcall() {}
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