Handle BUFIF logic when vector inputs
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d53014a07f
commit
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@ -139,6 +139,22 @@ vhdl_expr *vhdl_expr::resize(int newwidth)
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return resize;
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}
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vhdl_expr *vhdl_const_int::cast(const vhdl_type *to)
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{
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if (to->get_name() == VHDL_TYPE_SIGNED
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|| to->get_name() == VHDL_TYPE_UNSIGNED) {
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const char *fname = to->get_name() == VHDL_TYPE_SIGNED
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? "To_Signed" : "To_Unsigned";
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vhdl_fcall *conv = new vhdl_fcall(fname, new vhdl_type(*to));
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conv->add_expr(this);
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conv->add_expr(new vhdl_const_int(to->get_width()));
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return conv;
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}
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else
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return vhdl_expr::cast(to);
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}
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int vhdl_const_bits::bits_to_int() const
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{
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@ -71,8 +71,17 @@ static void bufif_logic(vhdl_arch *arch, ivl_net_logic_t log, bool if0)
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vhdl_expr *sel = nexus_to_var_ref(arch->get_scope(), ivl_logic_pin(log, 2));
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assert(val);
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vhdl_expr *on = new vhdl_const_bit(if0 ? '0' : '1');
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vhdl_expr *cmp = new vhdl_binop_expr(sel, VHDL_BINOP_EQ, on, NULL);
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vhdl_expr *cmp;
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if (ivl_logic_width(log) == 1) {
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vhdl_expr *on = new vhdl_const_bit(if0 ? '0' : '1');
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cmp = new vhdl_binop_expr(sel, VHDL_BINOP_EQ, on, NULL);
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}
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else {
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vhdl_expr *zero = (new vhdl_const_int(0))->cast(sel->get_type());
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vhdl_binop_t op = if0 ? VHDL_BINOP_EQ : VHDL_BINOP_NEQ;
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cmp = new vhdl_binop_expr(sel, op, zero, NULL);
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}
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ivl_signal_t sig = find_signal_named(lhs->get_name(), arch->get_scope());
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char zbit;
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@ -87,8 +96,10 @@ static void bufif_logic(vhdl_arch *arch, ivl_net_logic_t log, bool if0)
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default:
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zbit = 'Z';
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}
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vhdl_const_bit *z = new vhdl_const_bit(zbit);
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vhdl_expr *z = new vhdl_const_bit(zbit);
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if (ivl_logic_width(log) > 1)
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z = new vhdl_bit_spec_expr(NULL, z);
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vhdl_cassign_stmt *cass = new vhdl_cassign_stmt(lhs, z);
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cass->add_condition(val, cmp);
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@ -202,6 +202,7 @@ public:
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vhdl_const_int(int64_t value)
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: vhdl_expr(vhdl_type::integer(), true), value_(value) {}
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void emit(std::ostream &of, int level) const;
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vhdl_expr *cast(const vhdl_type *to);
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private:
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int64_t value_;
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};
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