Add regression tests for issue #1074.
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module test();
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bit [7:0] a;
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bit [7:0] b;
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bit [7:0] c;
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bit [7:0] d;
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assign a[7:4] = 4'b0010;
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assign b[7:6] = 2'b01;
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assign b[5:4] = 2'b10;
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assign c = 8'bx;
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assign d = c + b - a;
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initial begin
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#0 $display("%b %b %b %b", a, b, c, d);
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if (d === 8'b01000000)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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module test();
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bit [7:0] a;
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bit [7:0] b;
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bit [7:0] c;
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bit [7:0] d;
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assign a[7:4] = 4'b0010;
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assign b[7:6] = 2'b01;
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assign b[5:4] = a[5:4];
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assign c = 8'bz;
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assign d = c + b - a;
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initial begin
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#0 $display("%b %b %b %b", a, b, c, d);
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if (d === 8'b01000000)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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@ -32,6 +32,8 @@ br_gh710c vvp_tests/br_gh710c.json
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br_gh939 vvp_tests/br_gh939.json
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br_gh1018 vvp_tests/br_gh1018.json
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br_gh1029 vvp_tests/br_gh1029.json
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br_gh1075a vvp_tests/br_gh1074a.json
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br_gh1075b vvp_tests/br_gh1074b.json
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ca_time_real` vvp_tests/ca_time_real.json
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case1 vvp_tests/case1.json
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case2 vvp_tests/case2.json
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{
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"type" : "normal",
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"source" : "br_gh1074a.v",
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"iverilog-args" : [ "-g2009" ]
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}
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{
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"type" : "normal",
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"source" : "br_gh1074b.v",
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"iverilog-args" : [ "-g2009" ]
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}
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